Nippon Gakki Seizo Kabushiki Kaisha

Ascii Corporation

Yamaha Corporation

Shigemitsu Yamaoka

Takatoshi Okumura

Takatoshi Ishii

Kazuhiko Nishi

Ryozo Yamashita

Minoru Morimoto

Kenji Iwamoto

Ryo Kamiya

Hirokazu Kato

Masahiro Mukojima

Akitoshi Saito

Kazuyuki Ito

Takashi Nitatori

An object incorporated in image data is formed with a plurality of polygons. An object table defines each polygon by means of coordinates at an apex in a view coordinate system and the sound generated from the polygon. The sound source processor unit controls sound to be generated from each polygon according to the position and direction of the polygon when the object is viewed from a viewpoint.

Three-dimensional sound system

An electronic circuit with an operation self-control function includes an electronic circuit body. A temperature sensor and a temperature-setting circuit detect the temperature of the electronic circuit body as an operating parameter indicative of an operating condition of the electronic circuit body, and a clock/peripheral circuit control circuit operates to restrict the operation of the electronic circuit body according to the detected temperature, to thereby restrain heat generation of the electronic circuit body.

Electronic circuit with operation self-control function

A video display control system displays a multicolor animation pattern on a screen of a video display unit. The video display control system is mainly constructed by a video RAM (VRAM) and a video display processor (VDP). The VRAM stores animation pattern data, display position data and at least two color data. The VDP reads these data and makes an animation pattern image displayed in at least two colors at a display position on the screen. The animation pattern image, two colors and display position are determined by the animation pattern data, two color data and display position data. In another video display control system, the VRAM stores at least two sets of animation pattern data, display position data and color data. When displaying two animation patterns, the VDP effects a logical operation on the two color data with respect to the overlapping portion of the two patterns and makes the overlapping portion displayed in a new color corresponding to the operation result. When the animation patterns overlaps, the VDP can also deliver a collision signal in place of the logical operation, thereby enabling a CPU to recognize the position of the overlapping portion.

Video display control system for animation pattern image

A data processing system processes digital information representing, for example, an image and supplied at a lower transfer rate from a data source such as an optical disc unit, to produce data in such a form as to be efficiently used by a device of a higher transfer rate such as a CRT display unit. The digital information includes a plurality of groups of data each representing, for example, a portion or a window of the image and added with control data for defining characteristics thereof. While the digital information is read out at a constant entire transfer rate, the plurality of groups of data are transferred at respective transfer rates which vary with a lapse of time. The control data of each group of data is separated therefrom, and the group of data and the separated control data are stored into first and second memories. The groups of data stored in the first memory are processed in accordance with the results of analysis of the control data stored in the second memory to form data in such a form as to be efficiently used by the device of the higher transfer rate.

Data processing system

An image processing apparatus sequentially reads image data corresponding to an area to be displayed from an image memory by use of an access address. This image memory stores the image data corresponding to the display area and other image data for other uses. The access address for the image memory is determined by the image processing apparatus such that the access address is increased from the predetermined start address in response to a scanning of a display screen. When the access address reaches at a predetermined boundary address representative of an address of the last image data corresponding to the display area of the image memory, the access address jumps to a predetermined jump destination address (such as the start address). Hence, the display will be started from the jump destination address, whereby the other image data can be prevented from being used for the display or from being destructed.

Image processing apparatus

An image processing apparatus processes image data stored in a memory to thereby display an image on a display screen of a display unit under a control of a central processing unit (CPU). In one aspect of the invention, source data read from a source area of the memory are subjected to a rotation process and a logical operation and then converted to transfer data which will be written in a destination area of the memory by every word. In addition, first and last words within one line on the display screen are masked in accordance with predetermined first and second mask data. In another aspect of the invention, one of a wait mode and a not-wait mode is selected by wait control data outputted from the CPU. In the wait mode, the CPU is subjected to a wait state even in a memory read cycle. In the not-wait mode, the CPU is not subjected to the wait state normally in the memory read cycle. However, the CPU is subjected to the wait state in the not-wait mode while a reading operation of the memory has not been completed.

Apparatus for processing image data for displaying an image on a display

An image processing apparatus designed to interface with different monitors which processes image data read from a video random access memory (VRAM) so as to display an image corresponding to the image data on a screen of a display unit under a control of a central processing unit (CPU). The image processing apparatus at least provides a plurality of registers and a memory for storing several kinds of reference data for several kinds of predetermined modes. When one mode is selected from the predetermined modes, one of a color display and a monochromatic display is selectively performed on a screen of one of a color monitor and a monochromatic monitor or a screen of one of moniters each having different standard. The reference data corresponding to the selected mode are read from the memory and stored in the registers. When the selected mode is changed, reference data stored in requisite registers selected by newly selected mode are automatically rewritten by the reference data selected by the newly selected mode without exchanging programs of the CPU.

Image processing system interfacing with different monitors

A video display control system is capable of moving a part of a still image from a first display area to a second display area on a screen. The video display control system includes a memory composed of a plurality of memory locations for storing a plurality of display data representative of images of display elements on the screen. First and second registers retain first and second area data representative of the first and second display areas, and an address data generator generates from these area data first and second address data, the first address data indicating memory locations which store display data corresponding to the first display area, the second address data indicating second memory locations which store display data corresponding to the second display area. A reading circuit reads the display data in the first memory locations in accordance with the first address data, while a writing circuit writes the read display data into the second memory locations in accordance with the second address data. This video display control system further includes another reading circuit and an operation circuit. This reading circuit reads the display data in the second memory locations and feeds the read display data to the operation circuit which effects an operation such as a logical operation or a transparency processing on each pair of the display data read from the first and second memory locations.

Video display control system for moving display images

A video display processor (VDP) is connectable to an input control device such as a light pen and a mouse. The VDP comprises a counter circuit which is composed of an X counter and a Y counter. When a mouse mode is selected, X and Y pulse signals are supplied to the X and Y counters so that the contents of the X and Y counters represent the amount of movement of the mouse. When a central processing unit (CPU) connected to the VDP reads the contents of the X and Y counters in this mouse mode, the X and Y counters are reset. When a light pen mode is selected, the X and Y counters effect a count operation of a clock signal generated in the VDP in synchronism with the display of image on a screen so that the contents of the X and Y counters represents X-Y coordinates of a display element which is currently displayed on the screen. The CPU reads the contents of the X and Y counters in response to a light detection signal outputted from the light pen thereby to input the X-Y coordinates of the display element selected by the light pen. In a collision detection mode, the counter circuit effects the same counting operation as that effected in the light pen mode. The CPU reads the contents of the X and Y counters in response to a collision detection signal, which is generated by an associated circuit when animation patterns of the video image displayed on the screen overlap, thereby to input the X-Y coordinates of the collision position.

Video display processor

A video display control system displays a video image composed of a plurality of display elements on a screen of a video display unit. The system comprises a memory (VRAM) for storing a plurality of color codes each representing at least one display element and a video display controller (VDP). The VDP comprises a mode register for selecting one of normal display and transparency processing modes, display processing circuit for reading the color codes from the VRAM, a backdrop color register for storing a color code such as one representing a backdrop color, a detection circuit for detecting a predetermined color code from the color codes read by the display processing circuit, and a selector controlled by an output of the detection circuit. In the normal display mode, the selector outputs all color codes read by the display processing circuit to the display unit. In the transparency processing mode, the selector outputs the color codes read by the display processing circuit to the display unit when the predetermined color code is not detected, and outputs the color code contained in the backdrop color register to the display unit when the predetermined color code is detected. The VDP further comprises another detection circuit for detecting a second predetermined color code from the color codes outputted from the selector to output a control signal. And if the second predetermined color code is detected in the transparency processing mode, the display unit displays an image in accordance with an external video signal.

Video display control system

A video display processor (VDP) produces a video signal by which a black and white image of an increased gradation can be displayed on a video display unit. The VDP reads from a video RAM (VRAM) either color codes each representative of a color of each display element, or amplitude data representative of amplitudes of a video signal to be reproduced. When displaying an image based on the color codes, the color codes are converted by a color palette circuit into color data each composed of three primary color data, and then supplied to a digital color encoder. The digital color encoder multiplies each of the three color data by predetermined coefficients at proper phase timings to output data representative of three chrominance signals. This output data is summed by an adder circuit and then converted into an analog signal to be supplied to the video display unit as the video signal. When displaying an image based on the amplitude data, the color palette circuit converts the amplitude data into gradation data. The digital color encoder multiplies the gradation data by other proper coefficients so that data proportional in value to the gradation data are obtained at the output of the adder circuit. This data is converted into an analog signal to thereby reproduce the video signal.

Video display controller

There is provided a video display controller which can vertically and horizontally shift a whole video image displayed on a screen of a video display unit. The video display controller comprises an image data read circuit which reads the image data from a video RAM, a register into which data representative of amount of shift of the video image is stored by a central processing unit, and a first counter which cyclicly counts a clock signal. An adder adds the data contained in the register and a count output of the first counter, and at a timing determined by this addition result a predetermined value is preset into a second counter. This second counter counts the clock signal from the predetermined value, and the image data read by the image data read circuit is outputted to the video display unit at a timing in accordance with a count output of this second counter. The register, first counter, adder and second counter are provided in each of vertical and horizontal scanning control circuits.

A video display control system for displaying a video image on a screen of a video display unit. This video display control system basically comprises a VRAM (video RAM) and a video display processor (VDP). The VRAM has memory locations corresponding to display elements on the screen. The VDP includes a first register for receiving area information identifying a display area on the screen, an address generator for generating addresses of memory locations corresponding to the display area in accordance with the area information, and a memory accessing circuit for accessing the memory locations having the addresses. Therefore, the memory accessing operation through this VDP does not need a complicated support by a central processing unit. The VDP further comprises a second register for storing a color code supplied from an external device or read from the VRAM. Through this second register, the memory accessing circuit performs a memory accessing operation such as a transfer of color code between the external device and the VRAM, whereby color painting on a display area such as a rectangular area, dot and a line can easily be achieved. The VDP further comprises an operation circuit for effecting a certain operation on a color code in the second register and a color code in the VRAM and generating a new color code in accordance with the operation result. The operation-related color change on a display area can be achieved by storing the new color code in a corresponding memory location of the VRAM.

A digital color encoder for producing color TV signal comprises primary color image signal sources, a sampling signal generator, coefficient memories, multipliers and an adder. The primary color image signal sources provide digitized color image signals respectively of red, green and blue. The sampling signal generator generates a sampling clock having a frequency three times as high as that of the chrominence subcarrier and provide three phase sampling signals for 0.degree., 120.degree. and 240.degree. having a frequency as same as that of the chrominence subcarrier. The coefficient memories provide coefficients for 0.degree., 120.degree. and 240.degree. for the respective color of red, green and blue according to the formula of NTSC color picture signal. The respective color image signals are sampled at the sampling clock frequency and respectively multipled with the respective coefficients in the multipliers, and then added together in the adder. This a composite color video signal is synthesized without use of ordinary subcarrier modulators for B-Y and R-Y.

Growing community of inventors

Hamamatsu, Japan

Shigemitsu Yamaoka