Denso Corporation

Nippondenso Co., Ltd.

Shigemitsu Fukatsu

Masakiyo Sumitomo

Yasushi Higuchi

Tsutomu Kawaguchi

Ryoichi Kubokoya

Nobuyuki Ooya

Yukiaki Yogo

Kenji Shiratori

Akira Kuroyanagi

Takuya Okuno

Mitsutaka Katada

Akiyoshi Asai

Ryouichi Kubokoya

A semiconductor device includes a first conductivity-type drift layer, a second conductivity-type base layer formed in a front surface portion of the drift layer, a second conductivity-type collector layer formed in the drift layer and separated from the base layer, gate insulation layers formed on a surface of the base layer, gate electrodes individually formed on the gate insulation layers, an emitter layer formed in a front surface portion of the base layer, an emitter electrode electrically connected to the emitter layer and the base layer, and a collector electrode electrically connected to the collector layer. A rate of change in a gate voltage of a part of the gate electrodes is smaller than a rate of change in a gate voltage of a remainder of the gate electrodes. The emitter layer is in contact with only the gate insulation layers provided with the part of the gate electrodes.

Semiconductor device

In a semiconductor device, a trench gate has a bottom portion in a drift layer and a communication portion extending from a surface of a base layer to communicate with the bottom portion. A distance between adjacent bottom portions is smaller than a distance between adjacent communication portions in a x-direction. A region between adjacent trench gates is divided in a y-direction into an effective region as an electron injection source and an ineffective region which does not serve as the electron injection source. An interval L(&#x3e;0) of the ineffective region in the y-direction, a length Dof the communication portion in the z-direction, and a length Dof the bottom portion in the z-direction satisfy L&#x2266;2(D+D). The z-direction is orthogonal to a x-y plane defined by the x-direction and the y-direction which are orthogonal to each other.

Load-short-circuit-tolerant semiconductor device having trench gates

A semiconductor device includes a drift layer, a base layer on the drift layer, and trench gate structures. Each trench gate structure includes a trench reaching the drift layer by penetrating the base layer, a gate insulation layer on a wall surface of the trench, and a gate electrode on the gate insulation layer. A bottom portion of the trench gate structure is located in the drift layer and expands in a predetermined direction so that a distance between the bottom portions of adjacent trench gate structures is less than a distance between opening portions of adjacent trench gate structures in the direction. A thickness of the gate insulation layer is greater in the bottom portion than in the opening portion.

Semiconductor device and method of manufacturing the same

A semiconductor device having an offset-gate structure, which can achieve a release of an electric field concentration and a lowering a transistor resistance at the same time. A semiconductor device has the offset-gate structure in which an offset region, at which a gate portion is not formed, is formed between an end of the gate portion and a drain on a silicon substrate. Surfaces of a source, the drain and a gate electrode of the gate portion are silicides to reduce a transistor resistance. Whereas a surface of the offset region formed between the gate portion and the drain does not include silicide. to prevent a potential of an end portion of the gate portion from being identical to a potential of the drain due to silicide. Therefore, it can achieve a release of an electric field concentration and a lowering a transistor resistance at the same time.

Semiconductor device and method of manufacturing the same including an offset-gate structure

In a nonvolatile semiconductor memory, a floating gate electrode is disposed above a silicon substrate between source and drain regions, through a tunnel film, and a control gate electrode is disposed above the floating gate electrode through an insulating film. The substrate is grounded and at least two negative voltages are respectively applied to the control gate electrode, so that a voltage is applied to the tunnel film. In these cases, charge retention properties are evaluated. The voltages applied to the control gate electrode are controlled so that the voltage applied to the tunnel film does not exceed a voltage applied to the tunnel film during a memory operation. A charge retention property when no voltage is applied across the control gate electrode and the substrate, i.e., when no voltage is externally applied to the tunnel film, is estimated by the charge retention properties when the two voltages are applied to the control gate electrode.

Charge retention lifetime evaluation method for nonvolatile semiconductor memory

A floating gate of a semiconductor memory device has a gate bird beak on an end portion thereof. Further, a positional relationship between the floating gate and a drain is controlled such that a depletion layer formed within the drain in a non-selected state of the semiconductor memory device faces the gate bird beak without interposing the drain therebetween. Accordingly, drain disturbance can be efficiently prevented.

Semiconductor memory device

A P-type impurity is doped by oblique ion implantation into N-type impurity diffusion layers formed respectively on both sides of a gate electrode of a Pch MOS transistor, thereby canceling the impurity of at least a portion of an N-type region overlapped by the gate electrode, to thereby suppress a rise in the threshold voltage of the P-channel type MIS transistor due to the N-type impurity diffusion layer and suppress fluctuations in the amount of current that can be made to flow and the current-driving capacity.

MIS type semiconductor device and method for manufacturing same

The insulating ability of a semiconductor device of two-layer gate electrode structure, such as EPROM, is improved at the upper surface of the first gate electrode as well as at the upper and lower edge parts of the first gate electrode. A LOCOS film is formed on a semiconductor substrate, and a floating gate is formed by patterning. Next, the first oxide film is formed on the floating gate, and then the first oxide film is etched out. Subsequently, the second oxide film is formed on the floating gate, and a control gate is formed on the floating gate using the second oxide film as an inter-layer insulating film. As a result of these two oxidations of the first and second oxide films and the removal of the first oxide film, the asperity of the upper surface of the floating gate is removed, and the upper and lower edge parts thereof are shaped into a round form.

Manufacturing method for semiconductor device

The present invention is intended to provide a method of fabricating an EEPROM having excellent endurance characteristics. A work obtained by processing a substrate (1) by a wafer processing process including a passivating process and having a tunnel oxide film, an aluminum wiring film and a passivation film is subjected to a low-temperature heat treatment employing a processing temperature of about 250.degree. C. and a processing time on the order of 50 hr in a thermostatic oven (20) in the presence of nitrogen gas. The low-temperature heat treatment reduces trap sites produced in the tunnel oxide film by a plasma CVD process carried out to form the passivation film to repair the tunnel oxide film damaged by the plasma CVD process and to improve the endurance characteristics. The aluminum wiring film is not deteriorated by the low-temperature heat treatment because the low-temperature heat treatment employs a relatively low processing temperature.

Growing community of inventors

Okazaki, Japan

Shigemitsu Fukatsu