Oki Electric Industry Co., Ltd.

Shigemi Yoshioka

Atsushi Takasugi

Terumi Hiraoka

A serial access memory low in current consumption, capable of restraining an increase in a chip size even if memory capacity increases. The serial access memory has a first and a second memory arrays each having memory cells electrically connected to corresponding bit lines, signal lines provided in common between the memory arrays and electrically connected to the corresponding bit lines through first transfer circuits, write registers electrically connected to the corresponding signal lines through a second transfer circuit, a write bus electrically connected to the write registers through a third transfer circuit, an input circuit electrically connected to the write bus, read registers electrically connected to the corresponding signal lines through a fourth transfer circuit, a read bus electrically connected to the read registers through a fifth transfer circuit, and an input circuit electrically connected to the read bus.

Serial access memory

An object is to provide a serial access memory and a data write/read method applicable thereto and capable of reducing the test time of the serial access memory. After transferring the data stored in the memory cells MC to MCm connected with a word line WL to the read registers Rreg- to Rreg-m all at once, the data stored in the memory cells MC to MCm connected with a word line WL is transferred to the write registers Wreg- to Wreg-m all at once. The data stored in the read register is transmitted to an output means through read data buses RD, /RD. The data stored in the write register is transmitted to the output means through write data buses WD, /WD, an input/output means , and the second read data buses RD , /RD . The output means compares the data transmitted from the read data buses RD, /RD with the data transmitted from second data buses RD , /RD

Serial access memory and data write/read method

A serial access memory low in current consumption, capable of restraining an increase in chip size even if memory capacity increases. The serial access memory has a first and a second memory arrays each having memory cells electrically connected to corresponding bit lines, signal lines provided in common between the memory arrays and electrically connected to the corresponding bit lines through first transfer circuits, write registers electrically connected to the corresponding signal lines through a second transfer circuit, a write bus electrically connected to the write registers through a third transfer circuit, an input circuit electrically connected to the write bus, read registers electrically connected to the corresponding signal lines through a fourth transfer circuit, a read bus electrically connected to the read registers through a fifth transfer circuit, and an input circuit electrically connected to the read bus.

The present invention provides a serial access memory low in current consumption, which is capable of restraining an increase in chip size even if memory capacity increases. The serial access memory has a first and a second memory arrays a and b each having memory cells electrically connected to their corresponding bit lines BLia, signal lines CLi provided in common between the memory arrays a and b and electrically connected to their corresponding bit lines BLia through first transfer means Ha and Hb, write registers WRm electrically connected to their corresponding signal lines CLi through a second transfer means F, a write bus WD electrically connected to the write registers WRm through a third transfer means D, an input means L electrically connected to the write bus WD, read registers RRm electrically connected to their corresponding signal lines CLi through a fourth transfer means I, a read bus RD electrically connected to the read registers RRm through a fifth transfer means K, and an input means M electrically connected to the read bus RD.

There is provided a serial access memory and a data write/read method applicable thereto. The serial access memory is able to function as the prior art FIFO type serial access memory and as the prior art line access type serial access memory, too. This serial access memory is provided with a memory cell array , a write register group , a read register group , and a write/read register group . The write/read register group is made up of write/read registers WRreg- to WRreg-m. These write/read registers are prepared by the same number as that of memory cells (m pieces) connected with each of word lines WL to WLn, in the same way as the write registers Wreg- to Wreg-m forming the write register group and the read registers Rreg- to Rreg-m forming the read register group

A serial access memory includes a data transfer unit including a memory cell array having a plurality of memory cells arranged therein for storing data therein, a first transfer register electrically connected to the memory cell array through a first switching circuit and a second transfer register electrically connected to the first transfer register through a second switching circuit. The data transfer unit is provided so that when each of the first and second switching circuits is in an ON state, data passes through the first transfer register so as to be transferred from the memory cell array to the second transfer register and when the first switching circuit is in an ON state and the second switching circuit is in an OFF state, data is transferred from the memory cell array to the first transfer register.

Growing community of inventors

Yamanashi, Japan

Shigemi Yoshioka