Hitachi, Ltd.

Shigemi Adachi

Yukihiro Seki

Koichi Okazawa

Nobukazu Kondo

Ryuichi Hattori

Masaya Umemura

Takashi Moriyama

Kouichi Nakai

Hideki Osaka

Yoshitake Nakaosa

Yoshiki Fujioka

Information processing system, bus arbiter, and bus controlling method

An information processing system includes a first bus, a second bus, a plurality of modules connected to both buses, a bus arbiter for arbitrating a bus access request of a bus master, and a storage means for storing access data up to a predetermined amount for one of modules when access destination information indicates that said module is the access destination. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus access request when it performs an access operation, the bus arbiter refers to whether the predetermined amount of access destination information is fully stored in the storage means, and decides whether or not to give a bus access to the bus master.

Method and system for arbitrating a bus according to the status of a

In an information processing apparatus including a backboard having a bus for transmitting signals therethrough, at least one module, and a connector to connect the bus to the module, the backboard includes two terminators disposed respectively at both ends of the bus for providing matched termination according to a characteristic impedance of the bus to which the module is connected and a matching resistor disposed between the bus and the module. The matching resistor has a resistance value Rm represented as

Information processing apparatus and backboard having on backboard side

A method for emulating programs in a system includes a plurality of first and second data processors having different instruction word sets. An instruction which interrupts the operating system on the first data processor is defined. When the instruction is detected in a program running on the first data processor, it is determined whether or not the instruction is an instruction associated with an input/output macro instruction. If it is found, as a result of the determination, that this is the case, an interrupt is caused in a program running on the second data processor which controls the emulation, and the input/output macro instruction output from an emulated program is translated into an input/output macro instuction for the operating system, thereby implementing an emulation with a minimized overhead.

Emulation method

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Seto, Japan

Shigemi Adachi