Hitachi, Ltd.

Shigeko Yazawa

Katsuyoshi Kitai

Tadaaki Isobe

Yasuhiro Inagami

Yoshiko Tamaki

Teruo Tanaka

Tadayuki Sakakibara

Masao Furukawa

Yoshio Kiriu

Hitoshi Abe

Yasuhiko Hatakeyama

Toshimitsu Ando

Masanao Ito

Mihoko Hashiba

A store control method for a computer system having a storage with independently accessible plural store banks, plural access request controllers for issuing access requests to the storage, and a store controller for transmitting the access requests to each store bank. The store controller has an access request priority determining circuit of plural stages for selecting the access requests in the order of higher priority for each store bank so as to determine the order of priority between the access requests in multiple stages on the basis of the access requests. Further, plural priority control circuits of each stage are provided for stepwise performing control of priority of the main store access requests issued by the vector data processor for each of the store banks. Access is made to the main storage by assuring the order between the vector elements constituting vector data by allowing each first priority control circuit to send the access requests to the priority control circuit of next stage. Furthermore, the priority control circuit of the n-th stage sends the access request from the plural priority control circuits of the (n-1)th stage while assuring the order of the priority control circuits of the (n- 1)th stage.

Store control method with hierarchic priority scheme for computer system

A data processor having memory requesters to execute instructions, an instruction hold unit disposed for each resource to hold an instruction being executed in the resource and instructions to be executed therein, and execution control units to cause, in a case where an execution completion report of an instruction being executed in either one of the resources is received, an instruction held in an instruction hold unit corresponding to the resource to be immediately executed, thereby successively supplying the respective resources with data items to be employed for executions of the consecutive instructions in the resources.

Data processor having resources and execution start control for starting

A plurality of storage control units are employed in the storage control unit section; moreover, two requester modules are adopted in association with these storage control units. Each memory module is constituted with as many access bank groups as there are storage control units. The access bank groups operate in concurrent fashion and are accessible from any one of the storage control units. In the element assignment, a plurality of request control units in each requester module and a plurality of vector data controllers in each vector register unit are respectively assigned with serial numbers beginning from zero. For a vector data controller, a number assigned thereto is divided by the request module count to attain a remainder such that the vector data controller is assigned to a request module having a number identical to the value of the remainder. Furthermore, a request queue is disposed at a stage preceding each priority unit and a request send-out unit is arranged to store therein a state of the request queue and to control a request transmission from each request control unit. Addresses are assigned to the respective memory modules, bank groups, and banks according to skew schemes respectively suitable therefor.

Vector processor with a memory assigned with skewed addresses adapted

A storage control apparatus of a computer system having a plurality of transfer pipelines issuing access requests to a plurality of memory banks of a storage device. Each memory bank is independently accessible in response to an access instruction from a vector processing device. Each of the transfer pipelines includes a plurality of access request control devices to which the access instruction from the vector processing device is allocated in association with elements of a vector. The access request control devices simultaneously issue in response to an access instruction a plurality of access requests. Each transfer pipeline also includes a priority decision device which detects whether or not the access requests forecasted to be issued from the plural access request control devices contend with the access requests issued from the plural access request control devices of another transfer pipeline. In a case where it is detected that a contention takes place, processing of the access requests of another transfer pipeline effecting the succeeding access instruction is set to a wait state such that the access requests of the pertinent transfer pipeline effecting the preceding access instruction are preferentially processed.

Method and apparatus for controlling storage in computer system

Frames of digital data each representing a single picture of a video motion picture display are handled in a computer system with an extended memory operating in parallel with a computer system instruction processor and main memory to bypass the computer system input/output processor for continuously outputting the video information on a real time basis. The outputted data may be recorded continuously at a constant data rate for an entire motion picture worth of information or actually displayed on the video display on a real time basis. The extended storage has a memory larger than the main memory, where all of the frame data is stored and read out in high speed bursts to a buffer that continuously reads the data out of the buffer for outputting. At least a start command and a starting address in the extended memory are contained within the main memory to be read out and decoded by the instruction processor and computer system memory storage control, for transfer to the extended memory, where they are used to start the program, which includes extended memory control words stored in the main memory, which control words are decoded and executed in the extended memory in parallel with the computer system instruction processor. Addresses of succeeding frames are generated and decoded and used for fetching entirely within the extended memory, for memory areas according to indirect addressing. The extended memory has external data transfer and internal data transfer registers that hold command words for respective transferring programs that may be operated in parallel, with conflict between external transfer and internal transfer being decided in favor of external transfer to assure continuous data outputting.

Information processing system

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Hadano, Japan

Shigeko Yazawa