Hitachi, Ltd.

Shigeko Hashimoto

Tadaaki Isobe

Teruo Tanaka

Yasuhiro Inagami

Katsuyoshi Kitai

Naonobu Sukegawa

Yoshiko Tamaki

Tadayuki Sakakibara

Eiki Kamada

Masakazu Fukagawa

Kouki Uwano

Miki Miyaki

Kohki Uwano

Tatsuya Ichiki

A shared main memory type multiprocessor is arranged to have a switch connection type. The multiprocessor prepares an instruction for outputting a synchronization transaction. When each CPU executes this instruction, after all the transactions of the preceding instructions are output, the synchronization transaction is output to the main memory and the coherence controller. By the synchronization transaction, the main memory serializes the memory accesses and the coherence controller guarantees the completion of the cache coherence control. This makes it possible to serialize the memory accesses and guarantee the completion of the cache coherence control at the same time.

Multiprocessor synchronization and coherency control system

Each of processors in a multiprocessor system has a circuit for sending a synchronizing signal to a storage controller (SC) connected thereto when executing a synchronization instruction such as a start, end or barrier synchronization instruction. Each of the SCs has a circuit for notifying the corresponding processor of establishment of a synchronization upon detection of completion of a check to be made by an address management table FAA and of the issuing of necessary cache cancel requests corresponding to a store instruction issued before the synchronization instruction and upon recognition of the fact that all the processors have sent their synchronizing signals and that the issuing of all the cache cancel requests have been complete.

Parallel processor synchronization and coherency control method and system

In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for priority circuits incorporated in the storage control unit. Paths for priority switching signal issued in accordance with a number of requests as generated and types of instruction generating the requests are provided between the priority switching signal control circuits and the priority control circuit of the storage control unit, while paths for the priority switching signal as generated are provided between the priority control circuit and all the priority circuits.

Priority control with concurrent switching of priorities of vector

Interprocessor priority control system for multivector processor

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Hadano, Japan

Shigeko Hashimoto