Renesas Technology Corp.

Hitachi Device Engineering Co., Ltd.

Renesas Electronics Corporation

Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Shigeki Ueda

Masashi Horiguchi

Takesada Akiba

Toshikazu Tachibana

Kazuhiko Kajigaya

Masakazu Aoki

Hitoshi Tanaka

Jun Etoh

Tsugio Takahashi

Hiroshi Kawamoto

Hideharu Yahata

The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

Semiconductor memory circuit

The present invention provides a semiconductor memory capable of shortening a refresh cycle time and reducing power consumption at refresh. The semiconductor memory includes an address input circuit for generating each of internal address signals, a redundant judgement circuit for receiving the internal address signal therein and determining whether the corresponding address corresponds to an address for a defective word line of a plurality of normal word lines, and an address counter for generating refresh address signals for sequentially refreshing the plurality of normal word lines and redundant word lines. The redundant judgment circuit is deactivated upon refresh.

Semiconductor memory

A voltage limiter circuit is disposed in a semiconductor IC chip in order to reduce an operating voltage of an internal circuit of a scaled-down element. A small capacitance of a Vcc wiring by the disposition constitutes a resonance circuit together with an inductance of the Vcc wiring. Resonance at the resonance circuit causes large variation of a supply current and noise. An additional capacitance is connected between the Vcc wiring and a Vss wiring in order to suppress the variation and noise. The capacitance is formed by a PN junction and is connected in series to a damping resistance.

Semiconductor integrated circuit having voltage limiter circuit

Growing community of inventors

Hachioji, Japan

Shigeki Ueda