Other

Shigeki Sunada

Takashi Yamashita

Yoshifumi Takata

Takeru Matsuoka

Junko Izumitani

There are described a semiconductor device having multilayer wiring and a method for manufacturing the semiconductor device, wherein an interconnection hole for interconnecting an upper wiring layer to a lower wiring layer is formed correctly, thereby improving the reliability of multilayer wiring. A lower silicon oxide film, an upper silicon oxide film, and a silicon nitride film to be interposed therebetween are formed on a spin-on-glass (SOG) film. Enlarged openings for interconnection holes are formed only within the upper silicon oxide film while the silicon nitride film is used as an etch stopper, thereby preventing extension of the enlarged openings to the SOG film.

Semiconductor device, and method of manufacturing the same

A dielectric layer for capacitive element is formed on a lower electrode. An interlayer insulating layer is formed on the lower electrode and the dielectric layer for capacitive element. A plug hole reaching the dielectric layer for capacitive element is formed in the interlayer insulating layer. Upper electrodes are formed to fill in the plug hole and positioned opposite to the lower electrode with the dielectric layer for capacitive element interposed. The dielectric layer for capacitive element is in contact with the upper surface of the lower electrode at a region directly below the plug hole and a region outside the sidewall of the plug hole. Thus, a semiconductor device having a capacitive element with a greater capacitance which prevents diffusion of metal atoms from the lower electrode as well as a manufacturing method thereof are provided.

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Hyogo, Japan

Shigeki Sunada