Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Other

Panasonic Corporation

Shigeki Sawada

Tohru Saitoh

Koichiro Yuki

Teruhito Ohnishi

Takahiro Kawashima

Keiichiro Shimizu

Ken Idota

Tsuneichiro Sano

Koichi Hasegawa

Paul A Clifton

Takashi Furuta

A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.

Bipolar transistor and method for fabricating the same

In a semiconductor device functioning as a SiGeC-HBT, an emitter/base stacked portionis formed on a Si epitaxially grown layer. The emitter/base stacked portionincludes: a SiGeC spacer layer; a SiGeC core base layercontaining boron at a high concentration, a SiGe cap layer; a Si cap layer, and an emitter layerformed by introducing phosphorus into the Si cap layerand the SiGe cap layer

Semiconductor device

In a semiconductor device acting as an HBT, an emitter/base laminate portion is provided on a Si epitaxially grown layer in the SiGeC-HBT. The emitter/base laminate portion includes a SiGeC spacer layer, a SiGeC core base layer containing the boron, a Si cap layer, and an emitter layer formed by introducing phosphorous into the Si cap layer. The C content of the SiGeC spacer layer is equal to or lower than that of the SiGeC core base layer.

A method for producing a bipolar transistor and an MOS transistor of the present invention includes the steps of: forming a first insulation film in an MOS transistor region where the MOS transistor is to be formed and in a bipolar transistor region where the bipolar transistor is to be formed; forming a first conductive film and a second insulation film on the first insulation film; and removing the second insulation film, the first conductive film and the first insulation film from the bipolar transistor region.

Method of fabricating a Bi-CMOS IC device including a self-alignment

In a Bi-CMOS integrated circuit device, to reduce a collector-substrate junction capacitance in an NPN transistor and to reduce the step of forming an anti-punch-through layer of the N-channel MOS transistor. Using as a mask a resist pattern having windows made on an element isolation LOCOS film 113a, 113c and P-type well layer 106, impurities are ion-implanted to form a channel stopper layer 115a, 115b for element isolation of a NPN transistor and an anti-punch-through layer 115c for a N-channel MOS transistor. Thus, a sufficient element isolation withstand voltage can be assured while avoiding an increase in the collector-substrate capacitance of the NPN transistor which is due to the transverse diffusion of the channel stopper layer when an epitaxial layer, well layer and LOCOS film are formed. In addition, without increasing the number of steps, the drain-source withstand voltage of the N-channel type MOS transistor and the short channel durability can be improved.

Method of fabricating a semiconductor integrated circuit device

Formed on a p-type semiconductor substrate are bipolar transistors and CMOS transistors. A bipolar transistor has a base extraction electrode a side-surface of which is covered with an oxide layer, a silicon nitride layer, and a polysilicon layer. A CMOS transistor has a gate electrode a side-surface of which is covered with an oxide layer, a silicon nitride layer, and a side-wall layer. The silicon nitride layer on the side-surface of the base extraction electrode is formed by the same fabrication step that the silicon nitride layer on the side-surface of the gate electrode is formed.

Semiconductor integrated circuit apparatus and associated fabrication

A superhigh speed vertical transistor having an ultra thin base, a vertical NPN transistor having a reverse direction structure for composing an IIL, and a lateral PNP transistor similarly composing an IIL to be an injector are formed on a P-type silicon substrate 1 by self-aligned and integrated. The emitter leading-out part opening of the superhigh speed vertical NPN transistor and the collector leading-out part opening of the vertical NPN transistor having a reverse direction structure are self-aligned to the base leading-out electrode. In the epitaxial layer, the P-type intrinsic base layer of superhigh speed vertical NPN transistor is formed by impurity diffusion from the emitter leading-out electrode formed of polysilicon film, and the P-type base layer of the vertical NPN transistor having a reverse direction structure is formed by ion implantation. By thus forming the superhigh speed vertical NPN transistor having a reverse direction structure in self-aligned process, the superhigh speed vertical NPN transistor of self-aligned type and IIL device may be integrated on a same chip. Besides, by forming the intrinsic base layer of the vertical NPN transistor having a reverse direction structure deeper in junction than the base layer formed by impurity diffusion from the polysilicon emitter electrode for the superhigh speed NPN transistor of self-aligned type, the low concentration epitaxial layer part beneath the intrinsic base layer for composing the emitter of the vertical NPN transistor having a reverse direction structure may be made smaller, thereby avoiding lowering of the current gain of the vertical NPN transistor having a reverse direction structure and lowering of high speed operation of IIL device accompanying accumulation of minority carrier.

Semiconductor integrated circuit device with self-aligned superhigh

A superhigh speed vertical transistor having an ultra thin base, a vertical NPN transistor having a reverse direction structure for composing an IIL, and a lateral PNP transistor similarly composing an injector of an IIL are integrated on a P-type silicon substrate. The emitter leading-out part opening of the superhigh speed vertical NPN transistor and the collector leading-out part opening of the vertical NPN transistor having a reverse direction structure are self-aligned to the base leading-out electrode. Since both the superhigh speed vertical NPN transistor having a reverse direction structure and the superhigh speed vertical NPN transistor are self-aligned, the superhigh speed vertical NPN transistor and the IIL device may be integrated on the same chip. In addition, the intrinsic base layer of the vertical NPN transistor having a reverse direction structure is deeper in junction than the base layer of the polysilicon emitter electrode for the superhigh speed NPN transistor of self-aligned type.

A method of manufacturing a semiconductor device forms an intrinsic base layer by doping an impurity in the emitter polysilicon electrode into the intrinsic base region of the surface of a semiconductor substrate by heat treatment through the emitter lead-out part hole self-aligned to the base lead-out electrode. Thus, beneath the insulation film of the substrate surface between the base lead-out part hole and emitter lead-out part hole, the outer marginal part of the intrinsic base layer and the inner marginal part of the extrinsic base layer overlap uniformly. Still more, since the diffusion of the impurity by heat treatment is very fast in the polysilicon emitter electrode as compared with that in the silicon substrate, an extremely shallow intrinsic base layer may be formed.

Growing community of inventors

Kyoto, Japan

Shigeki Sawada