National Institute of Advanced Industrial Science and Technology

Agency of Industrial Science and Technology

Wacom R&d Corporation

Ministry of International Trade & Industry

Other

Agency of Industrial Science and Technology Ministry of International

Nippon Precision Circuits Inc.

Agency of Industrial Science & Technology, Ministry of International Trade & Industry

Seiko Npc Corporation

Wacom Corporation Limited

Agency Industrial Science & Technology, Ministry of International Trade & Industry

Shigeki Sakai

Mitsue Takahashi

Masaru Umeda

Masayuki Toda

Masaki Kusuhara

Shinji Migita

Kazuo Sakamaki

Yoshikazu Sasaki

Yuji Kasai

Wei Zhang

Ken Takeuchi

Shoei Kataoka

Hiroshi Tateno

Hiroshi Akoh

Akihiko Yagi

Shouyu Wang

Hisao Hayakawa

A FeFET and a method of its manufacture are provided, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm&#x3c;dr&#x3c;150 nm, without impairing the data retention property of not less than 10seconds and the data rewrite endurance property of not less than 10times, of those that have hitherto been developed, and the FeFET allowing a memory window of 0.40 V or more when a sweep amplitude of the gate voltage is not more than 3.3 V.

Method of making semiconductor ferroelectric memory element, and semiconductor ferroelectric memory transistor

A semiconductor memory element is provided including a laminated structure, in which a memory member and a conductor are superposed on a semiconductor substrate. The memory member has a bottom surface in contact with the semiconductor substrate, an upper surface in contact with the conductor, and side surfaces, which are in contact with and surrounded by a partition wall; the bottom surface of the memory member has a width of equal to or not more than 100 nm; a shortest distance between the conductor and the semiconductor substrate is twice or more of the width of the bottom surface of the memory member; the side surface of the memory member has a width, which is either the same as the width of the bottom surface and constant at any position above the bottom surface, or the widest at a position other than the bottom surface and above the bottom surface.

Semiconductor memory element, other elements, and their production methods

[Object] To provide a FeFET and a method of its manufacture, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm&#x3c;dr&#x3c;150, without impairing the data retention property of not less than 10seconds and the data rewrite withstand property of not less than 10times, of those that have hitherto been developed, and the FeFET allowing data to be written with a writing voltage whose absolute value is not more than 3.3 volts. [Means for Solving] In methods of making a device in which an insulator, a film made of constituent elements of a bismuth layered perovskite crystalline ferroelectric and a metal are sequentially formed in the indicated order on a semiconductor substrate and thereafter are annealed for ferroelectric crystallization, thereby preparing the device composed of the semiconductor, insulator, ferroelectric and metal, a method of making a semiconductor ferroelectric memory element in which the film is composed of Ca. Sr, Bi, Ta and oxygen atoms, the metal is Ir or Pt or an alloy of Ir and Pt, or Ru, and the annealing for ferroelectric crystallization is performed in a mixed gas having oxygen added to nitrogen or a mixed gas having oxygen added to argon.

Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body () and a gate electrode conductor () are sequentially laminated in this order on a semiconductor base () that has a source region () and a drain region (). The insulating body () is configured by laminating a first insulating body () and a second insulating body () in this order on the base (), and the second insulating body () is mainly composed of an oxide of strontium, calcium, bismuth and tantalum.

Semiconductor ferroelectric storage transistor and method for manufacturing same

A ferroelectric device and a manufacturing method are provided. While holding a nonvolatile memory retention capability and a multiple rewriting endurance as the distinctive features of a ferroelectric device, the disclosed ferroelectric device is wider in memory window and more adaptively made microfiner than a conventional ferroelectric device that has used a ferroelectric mainly constituted of Sr&#x2014;Bi&#x2014;Ta&#x2014;O as an oxide of strontium, bismuth and tantalum. Directly on or with intermediary of an insulator on a semiconductor there are layered a first ferroelectric and a conductor to form a gate stack, the first ferroelectric being mainly constituted of Sr&#x2014;Ca&#x2014;Bi&#x2014;Ta&#x2014;O as an oxide of strontium, calcium, bismuth and tantalum and being built up by a metal organic vapor deposition technique from a suitable film-forming raw material. The gate stack is heat-treated to cause the first ferroelectric to develop its ferroelectricity.

Ferroelectric device and method of its manufacture

There is provided a semiconductor integrated circuit including a state detection enhancement circuit which includes an input terminal and an output terminal and has a function of generating an electric potential of a magnitude capable of performing nonvolatile memory writing into a nonvolatile memory circuit based on an electric potential input to the input terminal and outputting the electric potential of the magnitude to the output terminal, and the nonvolatile memory circuit has a nonvolatile memory function and an input terminal of the nonvolatile memory circuit is connected to the output of the state detection enhancement circuit. The state detection enhancement circuit is a positive or negative logical state detection enhancement circuit which includes a control signal terminal and a switch circuit which is turned on or off by a control signal applied to the control signal terminal, and has a function of either applying an output potential of the same logical state as or an inverse logical state of an input potential applied to the input terminal to the output terminal or completely breaking off a correlation between the input potential and the output potential when the switch circuit is in an OFF state, and has a function of applying an output potential which has the same logical state as or an inverse logical state of the input potential and has a larger highest-lowest potential range including a possible highest-lowest potential range of the input potential to the output terminal when the switch is in an ON state.

Semiconductor integrated circuit

This invention has the purpose of providing a nonvolatile semiconductor storage device which is capable of entering multivalued storage in a FeFET unit without requiring preparation of a plurality of voltage sources. The nonvolatile semiconductor storage device is provided with multivalued ferroelectric memory cells which impart varied quantities of polarization to a ferroelectric material by applying pulse voltages having one and the same height and varied widths and consequently produce varied states of storage in conformity with the varied quantities of polarization.

Nonvolatile semiconductor storage device

A field-effect transistor for nonvolatile memory holding use and a field-effect transistor for logical operation use are manufactured in the same structure on the same semiconductor substrate without separately providing manufacturing processes for the field-effect transistors for the two uses. Both a memory circuit and a logic circuit of a semiconductor integrated circuit are composed of n-channel and p-channel field-effect transistors including a memory holding material in a gate insulating structure. A logical operation state, a memory writing state and a nonvolatile memory holding state are electrically switched by controlling the level and application timing of a voltage to be applied between a gate conductor and a substrate region of the n-channel and p-channel field-effect transistors including the memory holding material in the gate insulating structure.

To provide a semiconductor nonvolatile storage device capable of applying distributed voltage efficiently to a ferroelectric capacitor in a semiconductor nonvolatile storage device having an MFMIS structure without enlarging a memory cell area and a method of fabricating the same, a ferroelectric nonvolatile storage element is constructed by a structure successively laminated with a first insulator layer (), a first conductor layer (), a ferroelectric layer () and a second conductor layer () on a channel region and is constructed by a structure having a third conductor () and a fourth conductor () respectively laminated on a source region and a drain region, in which the third conductor () and the fourth conductor () are opposed to each other via the first conductor layer () and a second insulator thin film ().

Semiconductor nonvolatile storage element and method of fabricating the same

A method of forming film on a substrate, in which in a preliminary step information on film thickness deposited on a test substrate prepared for use in collecting information over a fixed irradiation time is obtained in advance while shining a laser beam on a target, there being a fixed positional relationship between spatial positions of the test substrate and an incidence point of the laser beam on the target, or while shining the laser beam on the target while rotating the test substrate. In a main step, a deposition time at each relative positional relationship is adjusted based on film-thickness distribution information obtained in the preliminary step while spatially moving or rotating the substrate or substrate holder about a specific central axis of rotation relative to the incidence point of the laser beam to the target, or while performing both the relative rotation and relative movement.

Method of forming film upon a substrate

The MFIS transistors heretofore have a problem that after data writing, the data disappear in terms of memory transistor operation in about one day at most. This is mainly because the buffer layer and the ferroelectric have a high leakage current and, hence, charge is accumulated around the interface between the ferroelectric and the buffer layer so as to shield the electric polarization memorized by the ferroelectric, making it impossible for the electric polarization of the ferroelectric to control electrical conduction between the source and the drain in the transistor. In the present invention, by constituting an insulator buffer layerof HfOor HfAlO, the leakage current flowing through each of the insulator buffer layerand a ferroelectriccan be reduced and a memory transistor having a truly sufficient long data holding time is realized.

Semiconductor-ferroelectric storage devices and processes for producing the same

A ferroelectric non-volatile memory device that allows the coupling ratio to be increased and the effect of voltage distribution to the ferroelectric capacitor to be improved without increasing the area of the gate electrode of a detection MIS field effect transistor is provided. In a memory cell structure, a semiconductor including regions for a source, a channel, and a drain, a gate insulator on the channel region, a floating gate conductor, a ferroelectrics, and an upper electrode conductor are layered in this order. The structure includes a paraelectric capacitor having one end connected to the floating gate conductor and the other end connected to the source region.

Ferroelectric non-volatile memory device having integral capacitor and gate electrode, and driving method of a ferroelectric non-volatile memory device

To provide a semiconductor nonvolatile storage device capable of applying distributed voltage efficiently to a ferroelectric capacitor in a semiconductor nonvolatile storage device having an MFMIS structure without enlarging a memory cell area and a method of fabricating the same, a ferroelectric nonvolatile storage element is constructed by a structure successively laminated with a first insulator layer ( ), a first conductor layer ( ), a ferroelectric layer ( ) and a second conductor layer ( ) on a channel region and is constructed by a structure having a third conductor ( ) and a fourth conductor ( ) respectively laminated on a source region and a drain region, in which the third conductor ( ) and the fourth conductor ( ) are opposed to each other via the first conductor layer ( ) and a second insulator thin film ( ).

An epitaxial compound structure has a crystal structure including fluorite crystal on which is epitaxially grown a film of simple perovskite crystal with a (011) orientation.

Growing community of inventors

Tsukuba, Japan

Shigeki Sakai