Denso Corporation

Shigeki Otsuka

Irina Kataeva

Takasuke Ito

Tomohiro Nezuka

Hironobu Akita

Yoshikazu Furuta

Kazuyoshi Nagase

Chao Chen

Naoto Kikuchi

A differential communication driver circuit includes a drive unit that drives differential signal lines connected via capacitors by a source current and a sink current. When a noise detection unit detects that in-phase noise is applied to the differential signal lines, a drive assisting unit maintains an amplitude of a differential signal output to the differential signal lines by increasing a current drive capability of the sink current.

Differential communication driver circuit

A method for adjusting output level of a neuron in a multilayer neural network is provided. The multilayer neural network includes a memristor and an analog processing circuit, causing transmission of the signals between the neurons and the signal processing in the neurons to be performed in an analog region. The method includes an adjustment step that adjusts an output level of the neurons of each of the layers, causing the output value to become lower than a write threshold voltage of the memristor and to fall within a maximum output range set for the analog processing circuit executing the generation of the output value in accordance with the activation function when each of the output values of the neurons of each of the layers becomes highest.

Method for adjusting output level of multilayer neural network neuron

The present disclosure describes an artificial neural network circuit including: at least one crossbar circuit to transmit a signal between layered neurons of an artificial neural network, the crossbar circuit including multiple input bars, multiple output bars arranged intersecting the input bars, and multiple memristors that are disposed at respective intersections of the input bars and the output bars to give a weight to the signal to be transmitted; a processing circuit to calculate a sum of signals flowing into each of the output bars while a weight to a corresponding signal is given by each of the memristors; a temperature sensor to detect environmental temperature; and an update portion that updates a trained value used in the crossbar circuit and/or the processing circuit.

Artificial neural network circuit and method for switching trained weight in artificial neural network circuit

A signal generation circuit includes: a capacitor charged and discharged by a current proportional to an input voltage; a switch controlling charging and discharging of the capacitor based on an output signal of a comparator that compares a feedback voltage according to an output voltage and a predetermined first reference voltage; a reference voltage generation unit generating a second reference voltage that is generated by adding an offset voltage proportional to the input voltage to an output proportional voltage proportional to the output voltage; and a comparator comparing a terminal voltage of the capacitor and the second reference voltage, and generates an ON-time signal based on an output signal of the comparator.

Switching power supply circuit

An artificial neural network circuit includes a crossbar circuit, and a processing circuit. The crossbar circuit transmits a signal between layered neurons of an artificial neural network. The crossbar circuit includes input bars, output bars arranged intersecting the input bars, and memristors. The processing circuit calculates a sum of signals flowing into each of the output bars. The processing circuit calculates, as the sum of the signals, a sum of signals flowing into a plurality of separate output bars and conductance values of the corresponding memristors are set so as to cooperate to give a desired weight to the signal to be transmitted.

Artificial neural network circuit

A image recognition system includes a first convolution layer, a pooling layer, a second convolution layer, a crossbar circuit having a plurality of input lines, at least one output line intersecting with the input lines, and a plurality of weight elements that are provided at intersection points between the input lines and the output line, weights each input value input to the input lines to output to the output line, and a control portion that selects from convolution operation results of the first convolution layer, an input value needed to acquire each pooling operation result needed to perform second filter convolution operation at each shift position in the second convolution layer, and inputs the input value selected to the input lines.

Convolutional neural network

A neural network circuit that uses a ramp function as an activation function includes a memory device in which memristors serving as memory elements are connected in a matrix. The neural network circuit further includes I-V conversion amplification circuits for converting currents flowing via the memory elements into voltages, a differential amplifier circuit for performing a differential operation on outputs of two I-V conversion amplification circuits, an A-D converter for performing an A-D conversion on a result of the differential operation, and an output determine that, by referring to input signals of the differential amplifier circuit, determines whether an output signal value of the differential amplifier circuit belongs to an active region or an inactive region. Based on a determination result, the input determiner switches over the differential amplifier circuit and the A-D converter between an operating state and a standby state.

Neural network circuit

A neural network circuit includes a memory device in which memristors being variable resistance elements are connected in a matrix and serve as memory elements of the memory device. The neural network circuit further includes a voltage application device arranged to apply a bias voltage to the memory device and current-voltage (I-V) conversion amplification circuits arranged to convert currents flowing via the memory elements into voltages and output the voltage. A feedback resistor of a respective I-V conversion amplification circuit includes a memristor. The feedback resistor of a respective I-V conversion amplification circuit and the memory elements acting as an input resistor of the I-V conversion amplification circuit are connected to align a polarity direction of the memristor of the feedback resistor and polarity directions of the memristors of the memory elements acting as the input resistor.

A neural network circuit includes: multiple storage portions that include a memristor; multiple D/A converters that receive data, causing a signal voltage to be applied to multiple voltage input terminals of the storage portions; multiple drive amplifiers that are connected between to the D/A converters and the voltage input terminals; multiple I/V conversion amplifiers that are connected to at least one current output terminal of the storage portions; multiple A/D converters; and a series circuit of a first switch and a second switch that is disposed in a feedback loop of each of the drive amplifiers; and a series circuit of a third switch and a fourth switch that is disposed in a feedback loop of each of the I/V conversion amplifiers.

A neural network circuit includes: a storage portion that includes memristors; D/A converters; drive amplifiers; I/V conversion amplifiers; A/D converters; and offset correctors. The offset corrector includes a first latch circuit, a second latch circuit, a subtractor that subtracts latch data, and a controller. In performing a bias setting operation, the controller controls a bias application amplifier to output the bias voltage, controls each of the D/A converters to cause the drive amplifier other than the bias application amplifier to output a reference voltage, and also cause the first latch circuit to latch the output data. In performing a normal operation, the controller controls the bias application amplifier to output the reference voltage, controls each of the D/A converters to cause the drive amplifier other than the bias application amplifier to output the signal voltage, and also cause the second latch circuit to latch the output data.

A short-circuit determination device is provided in a switching power supply device. The switching power supply device converts a power supply voltage applied between an upper power supply line and a lower power supply line and outputs the power supply voltage to a load through an intermediate node. The switching power supply device includes a plurality of upper switching elements and a lower switching element. Each of the plurality of upper switching elements has an electrical conduction terminal and a control terminal. The electrical conduction terminals are connected in series between the upper power supply line and the intermediate node. The control terminals are driven at a same level as each other. The lower switching element has an electrical conduction terminal connected between the lower power supply line and the intermediate node. The lower switching element and the plurality of upper switching elements are connected in series.

Short-circuit determination device and switching power supply device

A neural network circuit is provided. The neural network circuit includes a memory device including memristors connected in a matrix, a controller arranged to control a voltage application device to perform writing, deleting and reading data in the memory device, multiple current-to-voltage (I-V) conversion amplifier circuits arranged to convert currents flowing through the memory elements into voltages and outputting the voltages, and multiple current adjusters respectively corresponding to the I-V conversion amplification circuits, each current adjuster being arranged to adjust a total current value input to a corresponding I-/V conversion amplification circuit to zero.

A neural network circuit includes: a storage part that includes memristors in a lattice shape; a voltage application circuit that applies a bias voltage to the storage part; a controller that controls the voltage application circuit to perform to a selection element, writing, erasing, or reading; and multiple conversion amplification circuits that convert a current flowing into a voltage, and output the voltage.

A transmission-path degradation detection apparatus includes a transmission path of a transmission system and plural communication devices connected to the transmission path. A signal generation part is provided in one communication device of the plural communication devices for generating a pseudo-communication signal. A degradation detection part is provided in one communication device of the plural communication devices for detecting a degradation of the transmission path based on a reception of the pseudo-communication signal passing through the transmission path.

Transmission-path degradation detection apparatus

A signal output device is provided in a communication apparatus. The communication apparatus communicates with a different one of the communication apparatus using a single line. The signal output device includes a signal output unit. The signal output unit includes a first filter and a second filter. The first filter is provided by a Bessel filter. The second filter is provided by a Chebyshev filter or a Butterworth filter. The signal output unit outputs a signal which is obtained by passing a predetermined signal through the first filter and the second filter. The signal output from the signal output unit has a pass characteristic of the first filter and a pass characteristic of the second filter. A cutoff frequency of the first filter is set to be lower than a cutoff frequency of the second filter.

Growing community of inventors

Kariya, Japan

Shigeki Otsuka