Texas Instruments Corporation

Hitachi, Ltd.

Shigeki Numaga

Kiyoshi Nakai

Yukihide Suzuki

Takashi Inui

Shunichi Sukegawa

Hiroyuki Yoshida

Edison H Chiu

Takumi Nasu

Hideyuki Fukuhara

Yoshimitsu Tamura

Takeshi Honzawa

The objective of the invention is to provide a type of semiconductor memory device whose antifuse can be formed without any additional film manufacturing process. A first electrode is formed by a first polysilicon film,formed on semiconductor substrate,and a second polysilicon film,deposited on the surface of the first polysilicon film. The first electrode, a dielectric film formed on the surface of the first electrode, and a second electrode form capacitor,in the memory cell. An antifuse,with the same configuration as capacitor,is formed in the semiconductor memory device. Because there is no need to use an additional film, the manufacturing cost is low, and antifuse,can be easily arranged. It is also possible to form antifuse,by forming instead of depositing the second polysilicon film,on the surface of the first polysilicon film

Semiconductor memory device with antifuse

A spatial light modulator (10) of the DMD type having an array of memory cells (16) controlling an array of pixels (12). The memory cell array (16) has several integral, interleaved spare rows of memory cells MR (R1), MR (R2), and MR (R3), which can be selectively utilized to replace a defective row of primary memory cells. A fused row address mapping logic circuit (40) includes a network of fuses (F0-F12) and controls the implementation of memory cells, as well as the mapping of address signals to the memory cells as a function of inputs (R0-R11) received from a row decoder circuit (20). This circuit (40) is transparent to the row address decoder circuit (20). The present invention is suitable for large spatial light modulators compatible with high definition television (HDTV). High yield devices can be obtained with the present invention.

Spatial light modulator having redundant memory cells

A semiconductor memory device having reserve bit lines or word lines for replacing defective bit lines or word lines which can increase a defect relief probability and improve an operational margin. The reserve bit lines or word lines are provided approximately in a central portion of a memory mat. Because of a low probability of defect occurrence in the reserve word lines or bit lines, the probability of defect occurrence can be made low when a defective word line or bit line is replaced with a reserve word line or bit line.

Semiconductor memory device having plural memory mats with centrally

A word line driving circuit which effectively prevents ground noise during word line discharge along with accommodating the narrowing of pitch in the word lines by making the layout area of the word line driver small. The word line driving circuit includes n-type MOS transistor 14 and p-type MOS transistor 12. The drain terminal of n-type MOS transistor 14 and drain terminal of p-type MOS transistor 12 in word line driver 10 are connected to the base terminal of word line WLi. The output terminal of an output transistor driving circuit 16 is connected to the source terminal of p-type MOS transistor 12, and the output terminal of a first output transistor controlling circuit 18 is connected to the gate terminal. The output terminal of a second output transistor controlling circuit 20 is connected to the gate terminal of n-type MOS transistor 14, and a ground terminal 22 as a reference potential terminal for leading in the electric current is connected to the source terminal.

Word line driving circuit

Growing community of inventors

Amimachi, Japan

Shigeki Numaga