Ricoh Company, Ltd.

Shigeki Matsuoka

Akira Takata

Yukio Kadowaki

Shogo Nakamura

Daisuke Kosaka

Hiizu Okubo

Takayoshi Shimizu

Takao Jinzai

Satoshi Kono

A multilevel sense circuit includes a memory MOSFET having one of at least two different current carrying states and a pair of reference MOSFETs one of which has one of the two current carrying states and the other of which has the other current carrying state. A first current supplying circuit is connected to the memory MOSFET for supplying a predetermined amount of current thereto when the memory MOSFET is activated. A second current supplying circuit is connected to the pair of reference MOSFETs and also to the first current supplying circuit, such that twice the aforementioned predetermined amount of current is supplied to the pair of reference MOSFETs when the memory MOSFET is activated. A multilevel semiconductor memory device includes a MOSFET having a channel whose width is varyingly set by providing a non-inverting region in a selected area of the channel by ion implantation.

Sense amplifier for a ROM having a multilevel memory cell

A composite finite impulse response digital filter for use in an image processing apparatus or the like includes a plurality of sub-filters connected in series. In each sub-filter, a random access memory (RAM) is provided for storing an input data and a barrel shifter is provided for shifting the data to a least significant bit (LSB) or most significant bit (MSB) side over the number of shifts corresponding to a first control signal. Because of the provision of the barrel shifter in each sub-circuit, it is not necessary to shift a data input into an input terminal over a predetermined number of bits before storing into the RAM. Thus, the memory capacity of the RAM can be significantly reduced in size.

Composite finite impulse response digital filter

An adder has first through third switching circuits, a logic circuit and an adding circuit part. The first switching circuit is coupled between a carry bit input terminal and a carry bit output terminal. The second switching circuit is coupled between a first power source voltage and the carry bit output terminal, and the third switching circuit is coupled between a second power source voltage and the carry bit output terminal. The logic circuit controls the ON/OFF states of the first through third switching circuits so that only one switching circuit is turned ON responsive to two binary values which are to be added in the adding circuit part. The propagation time of a carry bit signal from the carry bit input terminal to the carry bit output terminal is constant regardless of the number of bits of the adding circuit part.

Adder having means for reducing propagation time of carry bit

A sense circuit for sensing a memory state of a memory transistor in a semiconductor memory device by determining whether the memory transistor is on or off is provided. The sense circuit includes a first load P-channel MOS transistor for supplying a first current to the memory transistor, a reference transistor capable of passing a second current same in magnitude as the on current of the memory transistor, and a second load P-channel MOS transistor for supplying the second current to the reference transistor, whereby the second load P-channel MOS transistor is operatively coupled to the first load P-channel MOS transistor.

Sense circuit

A system and method for programming an EPROM which includes a bit line, a plurality of memory cell MOS transistors connected to the bit line, a switching transistor for selectively applying a programming voltage to the bit line, and a selection circuit for selecting one of the memory transistors for programming. In accordance with the principle of the present invention, when one of the memory transistors is selected for programming, the programming voltage is applied to the bit line and thus to the drain of the selected memory transistor and to the gate of the selected memory transistor. Then, even after termination of application of the programming voltage to the bit line, the programming voltage remains to be applied to the gate for a predetermined time period, thereby allowing charge stored in the parasitic capacitance of the bit line to be completely discharged through the selected transistor.

Programming of an EPROM

A power supply switching circuit for supplying a pair of power supply voltages different in level, such as programming voltage V.sub.pp and reference voltage V.sub.cc, selectively is provided. The circuit includes a plurality of P-channel and N-channel MOS transistors which are appropriately connected such that no leakage or reverse current is produced even if the voltage at the V.sub.pp terminal becomes lower than V.sub.cc.

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Suita, Japan

Shigeki Matsuoka