Murata Manufacturing Co., Ltd.

Renesas Electronics Corporation

Murata Manufacturingco., Ltd.

Hitachi, Ltd.

Renesas Technology Corp.

Shigeki Koya

Yasunari Umemoto

Isao Obu

Takayuki Tsutsui

Masao Kondo

Kenji Sasaki

Yasushi Shigeno

Akishige Nakajima

Takashi Ogawa

Shinichiro Takatani

Atsushi Kurokawa

Shinnosuke Takahashi

Kaoru Ideno

Shaojun Ma

Masahiro Shibata

Yusuke Tanaka

Kazuhito Nakai

Shinya Osakabe

Hiroyuki Takazawa

Takashi Kitahara

Kingo Kurotani

Yuichi Saito

Satoshi Tanaka

Masayuki Aoike

Kaoru Katoh

Masatoshi Hase

Eigo Tange

Tsutomu Kobori

Shigeru Yoshida

Irei Kyu

Yoshimitsu Takenouchi

A power amplifier comprising amplifier circuits of multiple stages. Each of the amplifier circuits of multiple stages includes a bipolar transistor and a base electrode. The bipolar transistor included in each of the amplifier circuits of multiple stages includes a collector layer, a base layer placed on the collector layer, and an emitter mesa placed on part of the region of the base layer. The emitter mesa has a shape elongated in one direction in plan view. The base electrode includes a base main portion arranged in such a manner as to be separated from the emitter mesa with a gap in a direction orthogonal to a lengthwise direction of the emitter mesa in plan view. The base main portion has a shape elongated in a direction parallel to the lengthwise direction of the emitter mesa in plan view and is electrically connected to the base layer.

Power amplifier

A power amplification circuit includes first wiring supplied with a first signal having a first frequency, second wiring supplied with a second signal having a second frequency that differs from the first frequency, a first amplification circuit that amplifies the first signal supplied through the first wiring and supplies a first amplified signal to the second wiring, and a second amplification circuit that amplifies the signal supplied through the second wiring and outputs a second amplified signal.

Power amplification circuit

A power amplifier that includes a substrate, and an emitter layer, a base layer, and a collector layer laminated in this order on a major surface of the substrate includes an electrical insulator provided adjacent to the emitter layer, an emitter electrode provided between the substrate and both the emitter layer and the electrical insulator, a base electrode electrically connected to the base layer, and a collector electrode electrically connected to the collector layer. The emitter electrode, the electrical insulator, and the base layer are provided between the substrate and the base electrode in a direction perpendicular to the major surface of the substrate.

Each of cells arranged on a substrate surface along a first direction includes at least one unit transistor. Collector electrodes are arranged between two adjacent cells. A first cell, which is at least one of the cells, includes unit transistors arranged along the first direction. The unit transistors are connected in parallel to each another. In the first cell, the base electrode and the emitter electrode in each unit transistor are arranged along the first direction, and the order of arrangement of the base electrode and the emitter electrode is the same among the unit transistors. When looking at one first cell, a maximum value of distances in the first direction between the emitter electrodes of two adjacent unit transistors in the first cell being looked at is shorter than ½ of a shorter one of distances between the first cell being looked at and adjacent cells.

Semiconductor device

A semiconductor having transistors arranged side by side in one direction over a surface of a substrate and are connected in parallel. At least one passive element is disposed on at least one of regions between two adjacent ones of the transistors. The transistors each include a collector layer over the substrate, a base layer on the collector layer, and an emitter layer on the base layer. Collector electrodes are arranged in such a manner that each of the collector electrodes is located between the substrate and the collector layer of the corresponding one of the transistors and is electrically connected to the collector layer.

A first amplifier circuit in a preceding stage, a second amplifier circuit in a subsequent stage, and a ground external connection terminal are disposed on a substrate. The first and second amplifier circuits each include bipolar transistors, capacitive elements for the respective bipolar transistors, and resistive elements for the respective bipolar transistors. The bipolar transistors each include separate base electrodes, that is, a first base electrode for radio frequency and a second base electrode for biasing. The bipolar transistors of the second amplifier circuit include emitter electrodes connected to the ground external connection terminal. The minimum spacing between the first base electrode and an emitter mesa layer of at least one of the bipolar transistors of the second amplifier circuit is greater than the minimum spacing between the first base electrode and am emitter mesa layer of each of the bipolar transistors of the first amplifier circuit.

Radio-frequency power-amplifying element

A semiconductor package includes a module substrate having opposite top and bottom surfaces, a semiconductor chip provided with bumps and mounted on the top surface of the module substrate via the bumps, and a metal member having a top portion disposed at a level higher than the semiconductor chip with reference to the top surface of the module substrate and including the semiconductor chip in plan view and a side portion extending from the top portion toward the module substrate. The module substrate includes a first metal film disposed on or in at least one of the bottom surface and an internal layer of the module substrate. The first metal film is electrically connected to the bumps and reaches a side surface of the module substrate. The side portion is thermally coupled to the first metal film at the side surface of the module substrate.

Semiconductor package, semiconductor device, semiconductor package-mounted apparatus, and semiconductor device-mounted apparatus

A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.

Bipolar transistor and radio-frequency power amplifier module

A collector layer, a base layer, and an emitter layer that are disposed on a substrate form a bipolar transistor. An emitter electrode is in ohmic contact with the emitter layer. The emitter layer has a shape that is long in one direction in plan view. A difference in dimension with respect to a longitudinal direction of the emitter layer between the emitter layer and an ohmic contact interface at which the emitter layer and the emitter electrode are in ohmic contact with each other is larger than a difference in dimension with respect to a width direction of the emitter layer between the emitter layer and the ohmic contact interface.

A compound semiconductor device comprises a heterojunction bipolar transistor including a plurality of unit transistors, a capacitor electrically connected between a RF input wire and a base wire for each unit transistor of the unit transistors, and a bump electrically connected to emitters of the unit transistors. The unit transistors are arranged in a first direction. The bump is disposed above the emitters of the unit transistors while extending in the first direction. The transistors include first and second unit transistors, the respective emitters of the first and second unit transistors being disposed on first and second sides, respectively, of a second direction, perpendicular to the first direction, with respect to a center line of the bump extending in the first direction. The capacitor is not covered by the bump, and respective lengths of the respective base wires connected respectively to the first and second unit transistors are different.

Compound semiconductor device

A cavity elongated in one direction is formed in a protective film covering the conductive pattern of the topmost conductive layer of a multilayer wiring substrate. The cavity exposes part of the conductive pattern. A first via-conductor extends downward from the conductive pattern of the topmost conductive layer at least until that of a second conductive layer. Second via-conductors extend downward from the conductive pattern of the second or third conductive layer at least until that of a conductive layer one below. As viewed from above, the first via-conductor and the cavity partially overlap each other. At least two second via-conductors are disposed to sandwich the cavity therebetween. The difference between the smallest gap between the cavity and the second via-conductor at one side and that between the cavity and the second via-conductor at the other side is smaller than the smallest gap between the cavity and the second via-conductors.

Multilayer wiring substrate

A collector layer is disposed on a substrate. The collector layer is a continuous region when viewed in plan. A base layer is disposed on the collector layer. An emitter layer is disposed on the base layer. An emitter mesa layer is disposed on the emitter layer. Two base electrodes are located outside the emitter mesa layer and within the base layer when viewed in plan. The two base electrodes are electrically connected to the base layer. Two capacitors are disposed on or above the substrate. Each of the two capacitors is connected between a corresponding one of the two base electrodes and a first line above the substrate. Two resistance elements are disposed on or above the substrate. Each of the two resistance elements is connected between a corresponding one of the two base electrodes and a second line on or above the substrate.

Unit cell and power amplifier module

A collector layer, a base layer, an emitter layer, and an emitter mesa layer are placed above a substrate in this order. A base electrode and an emitter electrode are further placed above the substrate. The emitter mesa layer has a long shape in a first direction in plan view. The base electrode includes a base electrode pad portion spaced from the emitter mesa layer in the first direction. An emitter wiring line and a base wiring line are placed on the emitter electrode and the base electrode, respectively. The emitter wiring line is connected to the emitter electrode via an emitter contact hole. In the first direction, the spacing between the edges of the emitter mesa layer and the emitter contact hole on the side of the base wiring line is smaller than that between the emitter mesa layer and the base wiring line.

An electrically conductive sub-collector layer is provided in a surface layer portion of a substrate. A collector layer, a base layer, and an emitter layer are located within the sub-collector layer when viewed in plan. The collector layer is connected to the sub-collector layer. An emitter electrode and a base electrode are long in a first direction when viewed in plan. The emitter electrode overlaps the emitter layer. The base electrode and the emitter electrode are discretely located away from each other in a second direction orthogonal to the first direction. A collector electrode is located on one side in the second direction with respect to the emitter electrode and is not located on the other side when viewed in plan. A base line is connected to the base electrode in a manner so as to adjoin a portion other than longitudinal ends of the base electrode.

An amplifier IC mounted on a multilayer board includes input, output, and common terminals. The multilayer board includes common, input, and output terminals on board side. These terminals are connected to the corresponding terminals on device side via bumps. On the lower surface of the multilayer board, a lower surface common terminal is arranged at a location overlapping the common terminal in plan view. First, second, and third via conductors are sequentially arranged toward the lower surface common terminal from the common terminal. An input via conductor is connected to the input terminal on board side. In plan view, the area of the first common via conductor is larger than any one of the areas of the second and third common via conductors and the input via conductor. In plan view, the area of bump of the common terminal is larger than the area of bump of the input terminal.

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Nagaokakyo, Japan

Shigeki Koya