Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Shigeki Komori

Katsuhiro Tsukamoto

Shigeru Kusunoki

Masahide Inuishi

Takashi Kuroi

Tomohiro Yamashita

Hidekazu Oda

Shuichi Ueno

Katsuyoshi Mitsui

Takehisa Yamaguchi

Tomohiko Yamashita

The technology which can improve the performance of a MOS transistor in which all the regions of the gate electrode were silicided is offered. A gate insulating film and a gate electrode of an nMOS transistor are laminated and formed in this order on a semiconductor substrate. A source/drain region of the nMOS transistor is formed in the upper surface of the semiconductor substrate. The source/drain region is silicided after siliciding all the regions of the gate electrode. Thus, silicide does not cohere in the source/drain region by the heat treatment at the silicidation of the gate electrode by siliciding the source/drain region after the silicidation of the gate electrode. Therefore, the electric resistance of the source/drain region is reduced and junction leak can be reduced. As a result, the performance of the nMOS transistor improves.

Manufacturing method for forming all regions of the gate electrode silicided

A trench is formed on a primary surface of a semiconductor substrate, and is filled with trench material to separate the surface region of the semiconductor substrate into plural active regions. At least a portion of the surface of the trench material adjoining the semiconductor substrate is depressed by a predetermined depth with reference to the primary surface of the semiconductor device. Thus, prevented is a decrease in a drain current of a semiconductor device having a trench isolation structure.

Method of manufacturing semiconductor device having an improved isolation structure

A photoresist () is formed on an element isolation insulating film () so as to cover the upper and side surfaces of a polysilicon film (R) which functions as a resistance element. With the photoresist () as an implantation mask, n-type impurities () such as phosphorus are ion-implanted from a direction substantially normal to the upper surface of a silicon substrate (). The dose is in the order of 10/cm. Through this processing, an LDD region () of MOSFET is formed inside the upper surface of the silicon substrate () within a transistor forming region. The impurities () are also implanted in a polysilicon film (G). On the other hand, as the polysilicon film (R) is covered by the photoresist (), the impurities () are not implanted into the polysilicon film (R).

Manufacturing method of a semiconductor device capable of accurately setting a resistance value of a resistance element

A static semiconductor memory device capable of preventing soft errors is provided. The static semiconductor memory device includes: a silicon substrate having a p-type well region; a storage node; an n-type-low-concentration impurity region and a high-concentration impurity region formed in the surface of p-type well region and connected to storage node; and a p-type impurity region formed to have contact with high-concentration impurity region.

Static semiconductor memory device

A tunneling magnetoresistive storage unit (TMR unit) includes a hollow cylinder-shaped free-spin element having one open end, a columnlike fixed-spin element formed inside the cylinder-shaped free-spin element, and a thin insulator layer located between them. The spin direction in the fixed-spin element is fixed to a predefined circumferential direction of its column-shaped magnetic substance beforehand and a tunneling current is flowed between the free-spin element and the fixed-spin element. A rotating magnetic field produced as a consequence is used to set the spin direction in the cylinder-shaped free-spin element to one of its circumferential directions. This structure decreases the amount of electric current required for performing data write operation, also enabling miniaturization and a higher level of integration of the TMR unit and a magnetic random-access memory by employing such TMR units.

Tunneling magnetoresistive storage unit

A semiconductor device having a gate electrode structure including at least a metal film and a polysilicon film is disclosed. The polysilicon film of the semiconductor is doped with impurities several times so that an upper portion of the polysilicon film becomes higher in doping level than a lower portion of the same.

Semiconductor device and method of manufacturing the same

A magnetic random-access memory comprises a semiconductor substrate ( ) on which write word lines ( ) and bit lines ( ) intersecting each other are arranged, TMR elements ( ) formed individually in areas of intersection of the write word lines ( ) and the bit lines ( ), each TMR element ( ) being formed by stacking a free-spin layer ( ) whose magnetization direction is variable, a fixed-spin layer ( ) whose magnetization direction is fixed and an insulator layer ( ) placed between the first and second magnetic substance layers, and access transistors ( ). The TMR elements ( ) are located where word lines ( ) which serve as gates of the access transistors ( ) intersect the bit lines ( ) so that the word lines ( ) perform the functions of both write and read word lines. This arrangement reduces the complexity involved in creating a multilayer interconnection structure, simplifies the structure and manufacturing processes of the magnetic random-access memory, and enables its miniaturization and a higher level of integration.

Magnetic random-access memory

A conductive plug is formed in an interlayer insulation film and on an isolating layer which isolates semiconductor elements on a semiconductor substrate. The conductive plug electrically connects a pair of active regions of the semiconductor elements formed on the different sides of the isolating layer. Alternatively, a conductive plug is formed in an interlayer insulation film and on a conducive line formed on an isolating layer which isolates semiconductor elements on a semiconductor substrate. The conductive plug electrically connects the conductive line and an active region of the semiconductor element.

Semiconductor device having an improved plug structure and method of manufacturing the same

Semiconductor device having an improved isolation structure, and method of manufacturing the semiconductor device

A semiconductor device having a polish preventing pattern that can improve the planarity of an element formation region after the CMP method polishing is provided. To the shape of an element formation region, a loop-shaped element formation region dummy is formed in a uniform width and at a uniform distance from the edge of the element formation region to have a loop shape. That can prevent formation of such a portion that is on a line extended from a gap between polish preventing patterns as well as a large gap between an element formation region and a polish preventing pattern. Accordingly, local application of large pressure to an end of an element formation region is suppressed which is caused when a polishing cloth bends. As a result, the semiconductor device does not have a locally substantially etched portion. The planarity of the surface of an element formation region is maintained in the semiconductor device.

Semiconductor device comprising a polish preventing pattern

A semiconductor substrate is of a first conductivity type and has a retrograde well impurity concentration. A first of the first conductivity type and having a second impurity concentration with an impurity concentration peak is formed on a main surface of the semiconductor substrate. A first impurity layer of a third impurity concentration comes into contact with the underside of the retrograde well. The third impurity concentration is smaller than the impurity concentration peak of the first impurity concentration and the second impurity concentration. An element is formed on the retrograde well.

Semiconductor device having a retrograde well structure and method of manufacturing thereof

A dummy cell part &lt;31&gt; includes a capacitor &lt;311&gt; having a first end which is connected to one of a plurality of pads &lt;2&gt; and a P-N junction element &lt;312&gt; having a first end which is connected to one of the plurality of pads &lt;2&gt; and a second end which is connected to one of the plurality of pads &lt;2&gt;. A sense part &lt;32&gt; is connected to a second end of the capacitor &lt;311&gt;, for sensing a potential on the second end of the capacitor &lt;311&gt; and outputting the result of sensing to one of the plurality of pads &lt;2&gt;. Thus, a memory cell evaluation semiconductor device which can evaluate a single memory cell, a method of fabricating the same and a memory cell evaluation method are obtained.

Memory cell evaluation semiconductor device, method of fabricating the

In a semiconductor substrate of a semiconductor device, a plural impurity layers of the same conductivity type as the substrate are formed. An impurity region of an opposite conductivity type penetrates at least one of the impurity layers to a certain depth from the main surface of the semiconductor substrate. The bottom surface of the impurity region terminates between the impurity layers where the impurity concentration is lower. A contact conductor is led out from the impurity region.

Semiconductor device

A lower electrode of a capacitor for use in a semiconductor device includes a first semiconductor layer having a predetermined impurity concentration and a second semiconductor layer having an impurity concentration higher than that of the first semiconductor layer. As a result, intensification of an electric field at an end portion of the capacitor can be reduced. In addition, a word line is formed of a buffer layer and a main conductor layer to reduce a parasitic capacitance between the lower electrode of the capacitor and the word line.

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Hyogo, Japan

Shigeki Komori