Fujitsu Corporation

Fujitsu Vlsi Limited

Shigeki Harada

Masahiro Sugimoto

Nobutaka Shimizu

Takehisa Tsujimura

Yasumasa Wakasugi

Masataka Mizukoshi

Hirohisa Matsuki

Masashi Takenaka

Toshiyuki Motooka

Joji Fujimori

Tatsuharu Matsuda

Kunio Kodama

Toshiki Yoshida

Tatsuro Yamashita

Syuichirou Takahasi

A test board used for testing a semiconductor device provided with projection electrodes includes a main board and testing electrodes. The testing electrodes are provided on the main board, each projecting upwardly from the main board. When the semiconductor device is tested, the testing electrodes are electrically connected to the projection electrodes by insertion of the testing electrodes into the projection electrodes. The semiconductor device is mounted on the main board to test the semiconductor device through the testing electrodes.

Test board for testing a semiconductor device, method of testing the

A metallization layer structure containing, in order, an aluminum nitride ceramic base layer, an aluminum titanium nitride layer, a titanium layer, a heat-resistant metallic layer and a metallic layer for facilitating soldering and brazing. The aluminum titanium nitride layer is formed at the interface between the aluminum nitride ceramic base layer and the titanium layer by subjecting a laminate containing, in order, an aluminum nitride ceramic base layer, a titanium layer, a heat-resistant metallic layer and a metallic layer for facilitating soldering and brazing to a heat treatment within the range of 350.degree.-1000.degree. C. for 40 minutes.

Method of producing a metallization layer structure

A ceramic package type semiconductor device comprising: a ceramic substrate having a wiring pattern layer formed on a top surface thereof; at least one semiconductor element mounted on the ceramic substrate with a top face thereof facing downward and electrically connected to the wiring patttern layer; a metal cap having at least one through-hole corresponding to an external size of the semiconductor element and an end portion thereof soldered to the top surface of the ceramic substrate, so that a top surface of the metal cap and a bottom surface of the semiconductor element fitting into the through-hole form a flat plane: and a heatsink member comprising a plate portion which is soldered to the flat plane of the metal cap and the semiconductor element to complete a hermetic sealing of the semiconductor element.

Ceramic package type semiconductor device and method of assembling the

A semiconductor device includes a semiconductor chip, a substrate for supporting the semiconductor chip, a plurality of terminals provided on the substrate for external connections, a plurality of lead wires provided on the semiconductor chip for connections to the terminals, and a multilevel interconnection structure for connecting the plurality of terminals to the plurality of lead wires on the semiconductor chip. The multilevel interconnection structure includes at least a lower conductor layer provided on the substrate and patterned into a plurality of pattern portions connected electrically to the terminals, an insulator layer provided on the lower conductor layer, and an upper conductor layer provided above the insulator layer. The upper conductor layer is formed with a connection area immediately below the lead wires on the semiconductor chip when the semiconductor chip is mounted on the substrate, the upper conductor layer is patterned in the connection area into a plurality of conductor strips extending parallel with each other in correspondence to the lead wires, the insulator layer is provided with contact holes so as to connect electrically the conductor strips of the upper conductor layer with the pattern portions of the lower conductor layer. In the semiconductor device, each of the pattern portions in the connection area has an edge extending obliquely to the conductor strips of the upper conductor layer wherein the pattern portions are disposed so that a pair of adjacent pattern portions have respective edges opposing with each other and extending parallel with each other with a lateral gap extending therebetween.

Packaged semiconductor device

A ceramic package type semiconductor device comprising: a ceramic substrate having a wiring pattern layer formed on a top surface thereof; at least one semiconductor element mounted on the ceramic substrate with a top face thereof facing downward and electrically connected to the wiring pattern layer; a metal cap having at least one through-hole corresponding to an external size of the semiconductor element and an end portion thereof soldered to the top surface of the ceramic substrate, so that a top surface of the metal cap and a bottom surface of the semiconductor element fitting into the through-hole form a flat plane: and a heatsink member comprising a plate portion which is soldered to the flat plane of the metal cap and the semiconductor element to complete a hermetic sealing of the semiconductor element.

A metallization layer structure includes an intermediate layer formed on an aluminum nitride ceramics base. The intermediate layer contains aluminum titanium nitride. A titanium layer is formed on the intermediate layer. A heat-resistant metallic layer is formed on the titanium layer. A metallic layer for facilitating soldering or brazing is formed on the heat-resistant metallic layer.

Metallization layer structure formed on aluminum nitride ceramics and

A semiconductor device comprises a substrate, a semiconductor element mounted on the substrate, a cap having an opening smaller than the external size of the semiconductor element for covering the semiconductor element to provide a hermetic seal, and a heatsink member mounted on the cap to cover the opening and to make contact with the semiconductor element via the opening, so that heat generated by the semiconductor element is conducted directly to the heatsink member. A method of producing the semiconductor device comprises the steps of mounting the semiconductor element on the substrate, covering the semiconductor element by the cap which is fixed to the substrate, and mounting the heatsink member on the cap to cover the opening and to make contact with the semiconductor element via the opening.

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Kawasaki, Japan

Shigeki Harada