Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Socionext Inc.

Shigeki Fujii

Nobuo Higaki

Kazuya Furukawa

Kazushi Kurata

Tetsuya Tanaka

Tokuzo Kiyohara

Hideshi Nishida

Kozo Kimura

Hiroshi Kadota

Kunihiko Hayashi

Toshio Sugimura

Hiroyuki Morishita

Kazuyoshi Horiike

Hideyo Tsuruta

Koumei Kubota

Shintarou Nakatani

Kousuke Yoshioka

A display control system includes a display controller, and a single virtual frame-memory. The display controller controls a plurality of display devices physically separated from each other. The virtual frame-memory stores one or more screen images to be displayed on the plurality of the display devices. The display controller is configured to write, into the virtual frame-memory, a screen image to be displayed on and across at least two of the plurality of the display devices.

Display control system, display system, movable-body apparatus, display controlling method, and storage medium

A processor executes a plurality of tasks by switching a timeslot and iterating a plurality of timeslots. The processor includes a table in which tasks are defined in correspondence with timeslots. In the table, the number of timeslots to be held in one iteration is defined, for each of the timeslots a total time period during the predetermined number of iterations is designated, and a plurality of tasks are defined in correspondence with at least one of the timeslots. A timeslot is switched every time a predetermined period elapses. One task is selected and executed by referring to the table in correspondence with switching of timeslot.

Processor and program execution method capable of efficient program execution

A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

A data transfer apparatus according to the present invention has; a DMAC and another DMAC which transfer data by direct memory access among a plurality of buses; a command queue which holds, as a queue, commands for instructing the data transfer; a bus information obtainment unit which obtains the commands from the command queue; a grouping unit which groups the held commands, based on a source and a destination designated in each of the obtained commands; a schedule unit which decides an order of issuing the commands sequentially from a group having more command, as a priority; and a selector which selects a command to be issued according to the decided order.

Data transfer apparatus, data transfer method, and program

A decoding apparatus is provided with a decoder for receiving plural bit streams and decoding the respective bit streams to output decoded bit streams, and a decoding state holder for saving and restoring plural states of the decoder. The decoder selects a bit stream to be a target of decoding, from among the plural bit streams to be decoded, decodes the selected bit stream, performs saving and restoration of its state into/from the decoding state holder, outputs plural decoding results to the corresponding destinations, and completes a series of the processes mentioned above within a predetermined period of time corresponding to each bit stream. Therefore, the plural bit streams can be decoded apparently at the same time, by using a single decoder.

Decoding apparatus, decoding method, decoding program, and decoding program storage medium

A media processing apparatus includes an input/output processing unit that performs input/output processing that is asynchronously caused by external factors and a decode processing unit that operates in parallel with the input/output processing unit and mainly performs decode processing for a data stream stored in a memory. The input/output processing receives an asynchronous input of a data stream from outside, stores the data stream into the memory, and supplies a data stream stored in the memory to the decode processing unit. The decode processing unit includes a sequential processing unit and a routine processing unit. The sequential processing unit performs header analysis for compressed video data in the data stream and a complete decode for compressed audio data in the data stream. Based on the results of the header analysis, the routine processing unit performs all of the decoding of the compressed video data aside from the header analysis. In the sequential processing unit, the header analysis is given priority over the decoding of the compressed audio data.

Media processing apparatus that operates at high efficiency

Growing community of inventors

Neyagawa, Japan

Shigeki Fujii