Seiko Epson Corporation

Seiko Epson Corporaiton

Shigeki Aoki

Norio Koizumi

Yoichi Imamura

Yohichi Imamura

Hisanobu Ishiyama

Haruo Kamijo

A display unit of which inspection process to inspect a connector for faulty connection can be automated. The display unit comprises a display section, a display driver IC among a plurality of types of display driver ICs capable of driving and controlling the display section, and an MPU sending a command and display data to the display driver IC. The display driver IC comprises an ID setting circuit and a command decoder decoding the command from the MPU. The MPU reads an ID information so as to control the display driver IC among a plurality of types of display driver ICs according to the corresponding control contents in the storage section among the plurality of types of control contents for a plurality of types of display driver ICs.

Display unit, electronic device using the same, and method of inspecting the display unit

Display unit and electronic device including the same

A semiconductor device is equipped with a silicon substrate , a segment signal output section formed along a central portion of one edge in a longitudinal direction of the silicon substrate , common signal output sections formed along portions on both sides of the central portion, divided power supply sections formed opposite to the common signal output sections along the other edge in the longitudinal direction of the silicon substrate , RAMs formed between the power supply sections , and a control section

Semiconductor device

A semiconductor device is equipped with segment signal output terminals S -S that output segment signals, common signal output terminals C -C that output common signals, dummy terminals NC -NC , input terminals P -P , bi-directional shift registers that operate to output common output signals from the common signal output terminals C -C , a shift direction signal output circuit that controls the shift registers , a common direction scanning signal input control circuit , and a shift register connection control circuit

A display unit of which inspection process to inspect a connector for faulty connection can be automated. The display unit comprises a liquid crystal display section, a display driver IC driving the liquid crystal display section, a first board on which the display driver IC is mounted, an MPU sending a command and other information to the display driver IC, a second board on which the MPU is mounted, and a connector electrically connecting the first and second boards to each other. The MPU has a means for sending a test command in the test modes and reading the inspection result signal output from the display driver IC thereafter. The display driver IC comprises an interface circuit outputting and inputting a signal to and from the MPU, a command decoder decoding the test command input from the MPU via the interface circuit, and an inspection circuit outputting the inspection result signal in accordance with the signal from the command decoder. The MPU reads the inspection result signal that is input via the interface circuit and connector, whereby it is possible to judge when the connection of the connector is faulty.

A semiconductor integrated circuit has a reset signal generation circuit ( ) that generates a reset signal ( ) having a reset period based on a power-on reset signal ( ), and a latch circuit ( ) having an initialization circuit ( ) that initializes a latch output ( ) based on the reset signal ( ). The reset signal generation circuit ( ) has a delay circuit ( ) that can variably set a pulse width corresponding to the reset period of the reset signal ( ). An output line of the delay circuit ( ) is connected to a first pad terminal ( ). An output line of the initialization circuit ( ) is connected to a second pad terminal ( ). When the semiconductor integrated circuit is verified, the first and second pad terminals ( ) are brought in contact with a probe ( ). During this verification process, according to input/output loads of a tester that is connected to the first pad terminal ( ), the pulse width of the reset signal ( ) is set wider than that during the normal use when the pad terminals are not contacted with a probe.

Semiconductor integrated circuit, liquid crystal apparatus, electronic apparatus and method for testing semiconductor integrated circuit

An oscillation device includes a buffer device, a feedback device for feeding back an output of the buffer device to an input thereof and a charging device and a discharging device connected to the input of the buffer device. The charging device includes a first switching device that is turned on and off based on the output of the buffer device and a first current control device that controls the current flowing into the input of the buffer device through the first switching device. The discharging device includes a second switching device that is turned on or off based on the output of the buffer device and a second current control device that controls the current flowing out of the input of the buffer device through the second switching device. The first and second switching devices include first and second transistors and the first and second current sources that include third and fourth transistors. The oscillation device includes a bias circuit that controls at least the current ratio of the first and second current of the first and second current sources by controlling bias voltages applied to first and second bias terminals of the oscillation device.

Oscillators with charging and discharging circuits

There are provided a drive unit which can be adjusted to various mounting forms and which can be reduced in power consumption and scale, and an electronic equipment containing such a drive unit. When a control signal DIR is switched from L-level to H-level, a logical operation circuit comprising a plurality of logic gates changes a READ address A which is in turn outputted toward a display memory. More particularly, an inverted signal of the READ address A is outputted as a READ address B. Thus, an image displayed on a liquid crystal display panel is vertically inverted. The drive unit can be adjusted to various mounting forms for the liquid crystal display device. Where the display memory includes a code data memory and a CG-ROM, first and second logical operation circuits are provided for each of the code data memory and CG-ROM. The output of the CG-ROM is connected to a third logical operation circuit which performs the lateral inversion for each character. The vertical and lateral inversion can also be accomplished by providing a decoder which outputs a latch signal at different timing at each time when the control signal DIR is switched from one level to another.

Drive unit and electronic equipment

The present invention provides a matrix type display device which simplifies the process in a display signal generating circuit while relieving the load on an external CPU, and which arranges freely character and icon display areas while preventing the quality of display from being degraded by the shadow phenomenon and others. A display code memory stores character display codes and icon display codes for one image at a desired address arrangement. A pattern generating circuit transfers image patterns for the display codes to a display signal transferring circuit through a multiplexer. A decoder selecting device is responsive to a decoder select signal to select a decoder, thereby controlling voluntarily the timing of latch signal generation. Display signal input in the time division manner is latched in first and second latch circuits through the latch signal. Thereafter, the display signal is transferred to a signal electrode driving circuit through a line memory to display an image on a matrix panel.

Matrix type display device, electronic system including the same and

An oscillation device and a display data processing device adjust variables such as the duty ratio of the oscillation frequency, and control autonomously timings between components such as memories. First and second switching devices disposed within charging and discharging devices are turned on and off by an output of a MOS buffer, enabling adjustment of the frequency and duty ratio of an oscillation signal. Equivalent circuits are provided corresponding to display data RAM, CGROM, and address decoders, data is read sequentially from the display data RAM and the CGROM when an EIRAM signal is enabled, and a DLAT signal is stored in a driver circuit. The equivalent circuits enable each of EIROM, EILAT, and RS signals at points when the read data is confirmed or thereafter. When the RS signal is enabled, EIRAM and other signals are sequentially disabled and the display data RAM and other components switch to a precharge operation.

Oscillation device, display data processing device, matrix-type display

The present invention provides a matrix type display device which simplifies the process in a display signal generating circuit while relieving the load on an external CPU, which arranges freely character and icon display areas while preventing the quality of display from being degraded by the shadow phenomenon and others. A display code memory stores character display codes and icon display codes for one image at a desired address arrangement. A pattern generating circuit transfers image patterns for the display codes to a display signal transferring circuit through a multiplexer. A decoder selecting device is responsive to a decoder select signal to select a decoder, thereby controlling voluntarily the timing of latch signal generation. Display signal input in the time division manner is latched in first and second latch circuits through the latch signal. Thereafter, the display signal is transferred to a signal electrode driving circuit through a line memory to display an image on a matrix panel.

An objective of the present invention is to provide a power supply device, a liquid crystal display device, and a method of supplying power that can enable designs with lower power consumptions and can also enable higher display qualities. A first voltage Vx, which is a constant voltage, is generated by a first voltage generation portion in a voltage regulation portion. A second voltage Vy having a value independent of that of Vx is generated by a second voltage generation portion, and Vx and Vy are added by an adder portion to generate a regulated voltage Vreg. A control portion provides variable control of Vy within a voltage regulation range that is defined to include Vx. The regulated voltage Vreg is divided by a voltage divider portion within a multi-value voltage generation portion. The impedances of voltages V2 and V4 are converted by first impedance conversion portions (n-type OP-amps), and the impedances of voltages V1 and V3 are converted by second impedance conversion portions (p-type OP-amps).

Growing community of inventors

Suwa, Japan

Shigeki Aoki