Fujitsu Corporation

Other

Fasl LLC

Advanced Micro Devices Corporation

Shigekazu Yamada

Colin Stewart Bill

Tien-Chun Yang

Pau-Ling Chen

Ming-Huei Shieh

Takao Akaogi

Kazuhiro Kurihara

Darlene G Hamilton

Binh Quang Le

Yasushi Kasa

Edward V Bautista, Jr

Edward Franklin Runnion

A transmission transistor transmitting a drain voltage is connected to an electrically rewritable nonvolatile memory cell. An operation control circuit controls program operation for increasing a threshold voltage of the memory cell, and verify operation which is performed before and after the program operation in order to verify the threshold voltage of the memory cell. A drain switching circuit connects during the verify operation a gate of the transmission transistor to a first voltage line through which a first voltage is supplied, and it connects during the program operation the same to a second voltage line through which a second voltage is supplied. Since the second voltage can be supplied to the transmission transistor only by the switching operation (selecting operation) of the drain switching circuit, the program operation can be started shortly after the verify operation. This can shorten the data write time to the memory cell.

Nonvolatile semiconductor memory

A method for controlling gate voltage in a memory device is described. The method includes providing a circuit that is adapted to be coupled with the memory device. The circuit is for generating a reference voltage. The method further includes utilizing the reference voltage provided by the circuit to apply a voltage at a gate of the memory device. The voltage has a value corresponding to a temperature of the memory device. The method also includes retaining a proportional relationship between the reference voltage and the temperature of the memory device, regardless of the change in the temperature of the memory device. The reference voltage provides a substantially constant programming time for the memory device regardless of the temperature of the memory device.

Method to obtain temperature independent program threshold voltage distribution using temperature dependent voltage reference

A nonvolatile semiconductor memory device includes a memory cell array which includes memory cells and reference cells, the reference cells including a first reference cell and a second reference cell. A data discriminating control unit generates an average reference level based on a reference level supplied from the first reference cell and a reference level supplied from the second reference cell, and the data discriminating control unit determining whether data is zero or one by comparison of a read-out level of each of the memory cells with the average reference level. A reference cell setting unit performs program verification for each memory cell with respect to a threshold level of the first reference cell to obtain a distribution of threshold levels of the memory cells, and the reference cell setting unit setting a threshold level of the second reference cell based on the distribution of the threshold levels of the memory cells.

Nonvolatile semiconductor memory device

A ground structure for page read and page write for flash memory. An array structure of flash memory cells comprises a plurality of sectors. Each sector comprises I/O blocks plus reference arrays and an array of redundant cells. Each I/O block comprises sub I/O blocks. Each sub I/O block within an I/O block, as well as other structures including reference cells, redundant cells and edge structures is coupled to a unique ground reference signal. These unique ground reference signals may be selectively coupled to a system ground or a biased ground reference. This novel ground arrangement enables a page read operation in which one bit from each sub I/O block can be read simultaneously. In addition, one bit from each I/O block may be programmed simultaneously. Further, the ground reference voltage for cells of the array may be selectively adjusted to optimize operation.

Ground structure for page read and page write for flash memory

A nonvolatile semiconductor memory device comprises a memory cell array which includes memory cells and reference cells, the reference cells including a first reference cell and a second reference cell. A data judging control unit generates an average reference current based on a first reference current from the first reference cell and a second reference current from the second reference cell, and determines data of each of the memory cells by comparison of a read-out current of each memory cell with the average reference current. A control unit performs a program verification operation to each memory cell. A compensation current supplying unit supplies a compensation current to a bit line of a target memory cell when a leak current of a neighboring memory cell adjacent to the target memory cell exceeds a predetermined reference value during the program verification operation.

System to control a pre-charge level of a dual bit cell in a memory device. The system includes apparatus comprising a first terminal coupled between first and second memory cells, and a second terminal coupled to the second memory cell. The apparatus also comprises a mirror circuit coupled to the first and second terminals, wherein the mirror circuit operates to maintain the same voltage level on the first and second terminals.

System for control of pre-charge levels in a memory device

System to set threshold voltages in a memory device. The system includes apparatus to set voltage threshold levels of a plurality of memory cells in a memory device. The plurality of memory cells are coupled to a common word line. The apparatus includes a plurality of gates that are coupled between a voltage source and the plurality of memory cells, the gates include control inputs that receive control signals that open and close each gate, so that when a selected gate is closed, the voltage source is coupled to a selected memory cell and when the selected gate is open the current source is uncoupled from the selected memory cell. The apparatus also includes control logic that generates the control signals to open and close the gates to individually enable and disable programming of the voltage threshold of each of the memory cells.

System for setting memory voltage threshold

System to program core cells in a memory device without over-programming. The system includes a method for programming a voltage threshold (Vt) level of a core cell in a memory device. The method comprises steps of determining a desired Vt for the core cell, programming a portion of the Vt of the core cell using a selected programming strength, verifying that the portion of the Vt is successfully programmed, adjusting the selected programming strength, and repeating the step of programming, verifying, and adjusting until the Vt of the core cell is substantially equal to the desired Vt.

System for programming a flash memory device

A system for reducing the recovery time for the second read in the double-bit cell of a semiconductor memory device. For reading the second bit of the double-bit cell, in addition to swapping the source and drain terminals of a core cell, the source and drain terminals of corresponding double-bit reference cells are also swapped. The system includes a circuit that effects the swapping by providing a path to enable reading the cells in the reverse direction for the second bit read. The swapping enables the bits of the core cell to be accurately determined over the life of the device while at the same time reducing the recovery time needed for execution of the read of the second bit of the double-bit cell.

System for reading a double-bit memory cell

System for generating a reference current in a semiconductor device. The reference current is compared to an internal device current generated by an internal device circuit to verify operation of the device. The system includes a current generator that generates the reference current and is located within the semiconductor device, and a bias generator that is coupled to the internal device circuit. The bias generator generates a back bias current to offset variations to the reference current.

System for reference current tracking in a semiconductor device

The present invention discloses a voltage regulation method and system that provides a predetermined erase voltage to at least one wordline during a negative gate stress mode. A low-supply voltage negative charge pump is activated to generate a relatively high negative voltage. The relatively high negative voltage is regulated to the predetermined erase voltage by a regulator circuit. Regulation of the relatively high negative voltage is based on a variable reference voltage that is generated by a reference voltage circuit and directed to the regulator circuit. The predetermined reference voltage is capable of being varied within a first predetermined voltage range, thereby varying the predetermined erase voltage. The predetermined erase voltage is transferred to the wordlines by at least one decoder circuit during an erase operation.

Negative voltage regulation

The present invention discloses a wordline voltage regulation method and system that provides a predetermined voltage as a wordline voltage to a plurality of wordlines during read mode. A supply voltage (Vcc) is regulated and temperature compensated by a wordline driver circuit to provide the predetermined voltage that is lower in magnitude than the magnitude of the supply voltage (Vcc). The wordline driver circuit is activated by an activation circuit when the read operation is initiated. During the read operation, the wordline driver circuit maintains the predetermined voltage during variations in the supply voltage (Vcc) as well as variations in a process load supplied by the wordline driver circuit.

Wordline driver for flash memory read mode

When an array VT test mode is entered, a predetermined wordline voltage is generated by a wordline voltage supply and supplied to at least one decoder circuit and a voltage control logic circuit. The voltage control logic circuit generates a predetermined control voltage that is directed to the decoder circuits. The predetermined control voltage activates the decoder circuits. A particular decoder circuit is electrically selected to decode at least one respective wordline and transfer the predetermined wordline voltage to the respective wordline. The activated decoder circuits that are not electrically selected are not forward-biased.

Application of external voltage during array VT testing

A high voltage comparator circuit quickly identifies the voltage level of the predetermined voltages required for program operations. Through the series of transistors, the precise timing of when the predetermined voltages are at their operating voltage level is identified.

High voltage comparator

The present invention discloses a method for saving overhead programming time in a flash memory. In the preferred embodiment of the invention, a wordline voltage generation circuit and a bitline voltage generation circuit are electrically connected with a comparator circuit. During the programming operation, the comparator circuit compares a wordline programming voltage and a bitline enabling voltage generated by the voltage generation circuits to determine when the programming voltages reach a predetermined voltage level. Once the predetermined voltage level is reached, the comparator circuit sends an output signal to a state machine that initiates programming for at least one cell. The present invention provides advantages over prior methods of programming by reducing the time period that the state machine waits to initiate programming.

Growing community of inventors

Cupertino, CA, United States of America

Shigekazu Yamada