Tdk Corporation

Shigekazu Sumita

Keiji Koga

Yuji Kakinuma

Joichiro Ezaki

Takeshi Nomura

Masaaki Ikeda

Yukie Nakano

Kousuke Nishiyama

Michio Abe

The number of write circuit components, variations in a write current flowing through each write line, and the power consumption for write operation can be reduced. A first constant current circuit and a second constant current circuit (a transistor (Q) and a resistor (R), and a transistor (Q) and a resistor (R)) are shared among a plurality of current direction control portions (&#x2212;1,+1, . . . ). The constant current circuits are connected to each current direction control portion () through a first circuit selector switch (SW. . . , SW, SW+1, . . . ) and a second circuit selector switch (SW. . . , SW, SW+1, . . . ) disposed for each current direction control portion (). Moreover, a decode signal voltage is applied to the constant current circuits from a word decode line (X) (bit decode line (Y)) through the circuit selector switches (SW) and (SW).

Magnetic memory device, write current driver circuit and write current driving method

A magnetic memory device and a sense amplifier circuit capable of obtaining a read signal output with a high S/N ratio and reducing power consumption and a circuit space, and a method of reading from a magnetic memory device are provided. In a sense amplifier, transistors (A), (B) which are differential amplifiers are commonly connected to one constant current circuit () through switches () ( . . . ,+1, . . . ). Corresponding bit decode lines () ( . . . ,+1, . . . ) and a read selection signal line () are connected to the switches () ( . . . ,+1, . . . ). A read/write signal is transferred from the read selection signal line (), and the switches () operate according to a bit decode value and the read/write signal.

Magnetic memory device, sense amplifier circuit and method of reading from magnetic memory device

The present invention provides a magnetic memory device based on a novel driving method realizing reliable writing and a method of writing the magnetic memory device. Four parallel portions are formed in a pair of loop-shaped write lines (Xn) and (Yn). Magnetoresistive devices (A) and (B) disposed in the parallel portion in an upper stage construct a memory cell (Ev), and magnetoresistive devices (A) and (B) disposed in the parallel portion in a lower stage construct a memory cell (Od). When current in the direction from the drive point A to the drive point B is passed from the current drives () and (), the directions of the currents in the write lines (Xn) and (Yn) are aligned in the parallel portion of the memory cell (Ev) but are opposite to each other in the parallel portion in the memory cell (Od). In the memory cell (Ev), induced magnetic fields enhance each other, and the magnetization directions of the magneto-sensitive layers of the magnetoresistive devices (A) and (B) are anti-parallel with each other. In the memory cell (Od), the induced magnetic fields cancel each other out.

Magnetic memory device and writing method of the same

The present invention provides a magnetic memory device capable of performing reading operation with lower power consumption and at high read precision and a method of reading the magnetic memory device. Sense bit lines (A,B) are provided in a bit line direction for each pair of magnetoresistive devices (A,B) constructing a storage cell () and a read current is supplied. The read currents passed through the pair of magnetoresistive devices (A,B) flow to the ground via a sense word line (). Further, by providing a constant current circuit (B) commonly for plural sense word lines (), the sum of a pair of read currents passing through the pair of magnetoresistive devices (A,B) in one storage cell constant, and information is read from the storage cell () on the basis of the difference between the pair of read currents. By sharing the constant current circuit (B), variations in the sum of the pair of read currents can be reduced, and power consumption can be also reduced.

Magnetic memory device and method of reading the same

In a ceramic multilayer chip capacitor comprising alternately stacked internal electrodes of Ni or Ni alloy and dielectric layers, an oxide layer having a different composition from the dielectric layer is formed on the periphery of each internal electrode. The dielectric layer consists essentially of grains and a grain boundary phase, the percent area of the grain boundary phase being up to 2% of the area of a cross section of the dielectric layer. The capacitor is prepared by alternately stacking Ni or Ni alloy and a dielectric material in layer form, firing and then heat treating the stack under predetermined oxygen partial pressures. The dielectric material is a barium titanate base oxide material. The capacitor has a long effective life.

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Chuo-ku, Japan

Shigekazu Sumita