Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Shigehisa Yamamoto

Yasuhiro Kimura

Katsuya Shiga

Akihiro Koyama

Hajime Watanabe

Takanori Tanaka

Shuhei Nakata

Kazuya Konishi

Hidekazu Yamamoto

Yoichiro Mitani

Shoyu Watanabe

Yasukazu Mukogawa

Yukiyasu Nakao

Yu Nakamura

Keiji Yamauchi

Masafumi Katsumata

An epitaxial substrate includes a single-crystal substrate of silicon carbide, and an epitaxial layer of silicon carbide disposed on the single-crystal substrate. The epitaxial layer includes a first epitaxial layer disposed on the single-crystal substrate, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed on the second epitaxial layer. The first epitaxial layer has a basal-plane-dislocation conversion rate of less than 95%. The second epitaxial layer has a basal-plane-dislocation conversion rate of more than 98%.

Silicon carbide epitaxial substrate and silicon carbide semiconductor device

The present invention provides a method for manufacturing silicon carbide semiconductor apparatus including a testing step of testing a PN diode for the presence or absence of stacking faults in a relatively short time and an energization test apparatus. The present invention sets the temperature of a bipolar semiconductor element at 150&#xb0; C. or higher and 230&#xb0; C. or lower, causes a forward current having a current density of 120 [A/cm] or more and 400 [A/cm] or less to continuously flow through the bipolar semiconductor element, calculates, in a case where a forward resistance of the bipolar semiconductor element through which the forward current flows reaches a saturation state, the degree of change in the forward resistance, and determines whether the calculated degree of change is smaller than a threshold value.

Method for manufacturing silicon carbide semiconductor apparatus, and energization test apparatus

A method of verifying semiconductor integrated circuit reliability allows reliability verification of a large-scale semiconductor integrated circuit without any omission. Step S is to obtain a sum total (Cio) of inner-cell input/output load capacities in a selected cell on the basis of input and output load capacities registered in a cell library database ( A), and step S is to obtain wiring capacitance (Cic) between cells. In step S , the sum total (Cio) of inner-cell input/output load capacities and the wiring capacitance (Cic) between cells are added to obtain output-terminal load capacity (COUT). On the basis of the output-terminal load capacity (COUT), a failure rate (FOUT) of an intercellular interconnect line is obtained in step S , and a failure rate (Fcell) of inner-cell interconnect lines is obtained in step S from an equation registered in the cell library database ( A). Then, those failure rates (Fcell, FOUT) are added to obtain a total failure rate (Ftotal) in step S

Method of verifying semiconductor integrated circuit reliability and cell library database

A burn-in test method and apparatus and a semiconductor chip to be used in a burn-in test method that allow current stress to be imposed on every circuit node by varying a power supply voltage in pulse form, and thereby enables an efficient burn-in test. A burn-in test is performed efficiently by imposing current stress to every internal circuit by supplying the internal circuits of a semiconductor chip with a pulse Vcc voltage that varies from 0 V to a burn-in voltage Vbi. The burn-in test time can further be shortened by varying the Vcc voltage in pulse form in a range from a voltage that is higher than or equal to the threshold voltage Vth to the burn-in voltage Vbi or by setting the pulse waveform of the Vcc voltage in such a manner that a high-voltage period T is longer than a low-voltage period T .

Burn-in test method for a semiconductor chip and burn-in test apparatus therefor

To provide a burn-in method and device capable of accelerating burn-in also in a peripheral circuit portion and a logic circuit portion as well as a memory cell array portion. A high temperature stress is applied to a wafer to be an evaluation object (Step SP ). Next, a low temperature stress and an electric stress are applied to the wafer (Step SP ). Then, it is decided whether a predetermined stress is applied to the wafer or not (Step SP ). If a result of the decision at the Step SP is &ldquo;YES&rdquo;, it is decided whether a defective portion is generated in each chip of the wafer or not (Step SP ). Referring to a chip decided to have a failure generated thereon as a result of the decision at the Step SP , it is decided whether repair is executed for the defective portion or not (Step SP ). If a result of the decision at the Step SP is &ldquo;YES&rdquo;, the repair is executed for the defective portion (Step SP ).

Burn-in method and burn-in device

A semiconductor device testing method using a semiconductor device testing apparatus that can improve the contact characteristic between probe needles and power-supply terminals and signal terminals while ensuring efficiency of product utilization of a tested wafer. Provided on a probe wafer (4) are bumps (5) formed in the same positions in mirror symmetry as the positions of pads (3) formed in individual chips (2) on a tested wafer (1), a common interconnection (6) for interconnecting bumps (5) to be supplied with the same power supplies and signals, and terminals (7) connected to the common interconnection (6) to supply power supplies and signals to the common interconnection (6) from the outside. The bumps (5) come in contact with the pads (3) in the chips (2) when the probe wafer (4) and the tested wafer (1) are put together. The common interconnection (6) supplies the power supplies and signals for a burn-in test to the pads (3) in the chips (2).

Method of testing semiconductor devices

An object is to obtain a semiconductor device testing apparatus that can improve the contact characteristic between probe needles and power-supply terminals and signal terminals while ensuring efficiency of product utilization of a tested wafer. Provided on a probe wafer (4) are bumps (5) formed in the same positions in mirror symmetry as the positions of pads (3) formed in individual chips (2) on a tested wafer (1), a common interconnection (6) for interconnecting bumps (5) to be supplied with the same power supplies and signals, and terminals (7) connected to the common interconnection (6) to supply power supplies and signals to the common interconnection (6) from the outside. The bumps (5) come in contact with the pads (3) in the chips (2) when the probe wafer (4) and the tested wafer (1) are put together. The common interconnection (6) supplies the power supplies and signals for a burn-in test to the pads (3) in the chips (2).

Semiconductor device testing apparatus and testing method thereof

An electric work station calculates an output load of a selected cell based on information from at least one of a design cell information library, a logic circuit information library and a layout information library. The work station further calculates a hot carrier dependent lifetime of a transistor in the cell by using the computed output load and information from a reliability information library, and verifies reliability of the cell by comparing the calculated lifetime with a reference value.

Design aiding apparatus and method for designing a semiconductor device

Center-to-center spacings (L.sub.1, L.sub.2, L.sub.3, L.sub.4, . . . ) of adjacent holes (5) in a hole chain (6) are set to values not less than five times a Blech length. This setting causes two parameters (MTF and .sigma.) of a logarithmic normal distribution used as a failure distribution for EM lifetime prediction to be constant independently of the center-to-center spacings, permitting stable EM lifetime prediction of the hole chain. Further, setting the length of each of extension interconnect wires (2) to a value not greater than the Blech length prevents voids from being created in the extension interconnect wires (2).

Device for evaluating reliability of interconnect wires

A semiconductor substrate with no reduction in the effective usage area and mechanical strength, and non-uniformity of the resist film thickness, and method of manufacturing and using the same are obtained. A detection mark for detecting the crystal orientation of a silicon wafer having an outer perimeter entirely of a circular contour is formed at a predetermined region of the silicon wafer. The crystal orientation of the semiconductor wafer can easily be detected with the outer perimeter still taking a circular contour. Therefore, various problems encountered in a conventional semiconductor substrate having an orientation flat or notch such as reduction in mechanical strength and effective usage area, and non-uniformity of the resist film can be circumvented.

Crystal orientation detectable semiconductor substrate, and methods of

An input protection circuit comprises an internal circuit and an input terminal, between which a pair of rectifying devices are interposed with polygonal diffusion regions of one and the other conduction types, which diffusion regions are formed longer along the width thereof orthogonal to the direction of current flow in the wiring than along the direction of current flow. The width of the contacts between said wiring and said diffusion regions is greater than the width of the wiring not having the contacts, thereby achieving a high electrostatic breakdown voltage.

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Tokyo, Japan

Shigehisa Yamamoto