Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Mitsubushi Denki Kabushiki Kaisha

Shigehiro Kuge

Kazutami Arimoto

Kiyohiro Furutani

Takeshi Hamamoto

Tadaaki Yamauchi

Shuichi Ueno

Taku Ogura

Satoshi Kawasaki

Minoru Senda

Masaki Tsukude

Kazuyasu Fujishima

Hiroshi Kato

Tsukasa Ooishi

Hideto Hidaka

Takashi Kubo

Takashi Kono

Fukashi Morishita

Shigeki Tomishima

Hideyuki Noda

Takahiro Tsuruda

Tetsushi Tanizaki

Shigeru Kikuda

Haruo Furuta

Tetsuo Kato

Shigeru Yamaoka

Katsuya Furue

In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of &#x2212;9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

Semiconductor device with pump circuit

A memory cell of a nonvolatile semiconductor memory device is formed on a silicon layer formed on a silicon substrate through an ONO film. The memory cell has a source region and a drain region formed in the silicon layer, an ONO film and a gate electrode. The ONO film and the ONO film include nitride films having charge trap parts trapping charges.

Nonvolatile semiconductor memory device

A plurality of semiconductor integrated circuits and a plurality of TEG circuits are aligned and provided on a substrate. In the TEG circuit, a built-in test circuit is provided in a region which faces a semiconductor integrated circuit across a dicing line region. The built-in test circuit and the semiconductor integrated circuit are connected by an interconnection which is provided on the dicing line region. The interconnection is cut for isolation into chips.

Semiconductor device capable of shortening test time and suppressing increase in chip area, and method of manufacturing semiconductor integrated circuit device

A semiconductor device is provided which includes a diode formed of a MISFET and having a current-voltage characteristic close to that of an ideal diode. Negatively charged particles (e.g. electrons:) are trapped on the drain region () side of a silicon nitride film () sandwiched between films of silicon oxide (). When a bias voltage is applied between the drain and source with the negatively charged particles () thus trapped and in-channel charged particles () induced by them, the MISFET exhibits different threshold values for channel formation depending on whether it is a forward bias or a reverse bias. That is to say, when a reverse bias is applied, the channel forms insufficiently and the source-drain current is less likely to flow, while the channel forms sufficiently and a large source-drain current flows when a forward bias is applied. This offers a current-voltage characteristic close to that of the ideal diode.

Semiconductor device

Data indicating whether a short-circuit defect exists in a memory block is programmed a fuse program circuit. In accordance with the fuse program data and a mode instruction signal, the correspondence relationship between a block select signal and a corresponding bit line isolation instruction signal is switched by a circuit that generates the bit line isolation instruction signal in a specific mode. It becomes possible to isolate the memory block in which a leakage current path exists from a corresponding sense amplifier band in a specific operation mode. Current consumption at least at a standby state is reduced.

Semiconductor memory device with reduced current consumption during standby state

This DDR SDRAM includes a test mode entry signal generation circuit which sets a test mode entry signal at &ldquo;H&rdquo; level in accordance with a consecutive input of a first command, a second command, a test mode entry set command, a third command and a test mode register set command synchronously with a rising edge of a clock signal. This enables the DDR SDRAM to enter a test mode without using a high voltage. The DDR SDRAM can, therefore, enter the test mode even if it is incorporated into a registered DIMM.

Semiconductor memory device having test mode and memory system using the same

The semiconductor memory device has a formal mode and a test mode as operating modes. The program circuit includes a fuse element in which an address using a spare memory cell instead of a defective memory cell is programmed. The program circuit confirms a disconnection state of a fuse in a condition severer in the test mode than that in the normal mode. An anomaly is notified to outside by a detection circuit in a case where results are different between the test mode and the normal mode. In a case where a fuse is not completely blown, such a fuse can also be detected in the test mode to exclude a defective chip.

Semiconductor memory device with enhanced reliability

An output drive circuit is constructed by an output driving MOS transistor driving an output node in accordance with an internal read data, a termination controlling P-channel MOS transistor selectively rendered conductive in accordance with the internal read data when the output driving MOS transistor is non-conductive, and a P-channel MOS transistor rendered conductive to pull up the output node to a power supply voltage level at least when the output drive circuit is inactive. Data transfer is executed in an open drain manner, and the P-channel MOS transistor is utilized as a transistor for termination bus line. Data/signal is transferred fast in an active termination scheme with low current consumption, and an area occupied by the output drive circuit is reduced.

Interface circuit and semiconductor device with the same

A nonvolatile semiconductor memory device includes a silicon substrate, bit lines, word lines, and memory cells. The bit line is positioned above the main surface of the silicon substrate and the word line is provided to intersect the bit line. The memory cell is positioned at a region where the bit line and the word line intersect and has one end electrically connected to the bit line and the other end electrically connected to the word line. The memory cell includes a TMR element and an access diode electrically connected in series. The access diode includes an n-type silicon layer and a p-type silicon layer recrystallized by melting-recrystallization and has a pn junction at the interface between the n-type silicon layer and the p-type silicon layer. As a result, a nonvolatile semiconductor memory device reduced in size and having high performance can be manufactured inexpensively.

An interface unit includes a timing control circuit for extracting an effective data window by detecting a point of change in a transferred data, and determining strobe timing for taking in the data in accordance with the extracted effective window; and a strobe clock generating circuit for generating a strobe clock signal for taking in the data under control of the timing control circuit. Regardless of the system structure, accurate data transfer is achieved between any semiconductor devices in the system.

Interface circuit device for performing data sampling at optimum strobe timing by using stored data window information to determine the strobe timing

A memory processing system according to the embodiment includes a system controller and a plurality of memory modules. The controller and the memory module transmit data from each other employing a data transmission line which is terminated only at an end at the side of the memory module. The memory chip monitors a reflected wave obtained at the time of data output to the data transmission line, thereby measuring the length of the data transmission line. Based on the measurement result, the system controller determines set up time/hold time for each memory chip.

Semiconductor integrated circuit having circuit for data transmission distance measurement and memory processing system with the same

A DLL circuit includes a delay circuit for producing an output clock signal by delaying an input clock signal, and a phase comparator circuit for making a comparison between phases of the output and input clock signals. The delay circuit includes a plurality of delay units each having a unit delay amount changing in accordance with a drive potential level. The DLL circuit further includes a delay control circuit for controlling activation of the delay units in accordance with the result of phase comparison of the phase comparator circuit, and a drive potential control circuit for controlling the drive potential in accordance with the result of phase comparison of the phase comparator circuit.

Clock generating circuit ensuring a wide lock-allowing frequency range and allowing reduction in layout area as well as a semiconductor device provided with the same

Internal parameter control signal generating units generate internal parameter control signals for adjusting internal parameters of a semiconductor memory device. Each internal parameter control signal generating unit includes an anti-fuse element formed with a data holding capacitor of a memory cell. The anti-fuse element is blown with application of a high voltage according to a parameter adjustment signal to break down a dielectric film and then, act as a resistance element. The internal parameter control signal generating unit sets a signal level of a corresponding internal parameter control signal in a non-volatile manner according to the presence or absence of a blowing input to the anti-fuse element.

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Hyogo, Japan

Shigehiro Kuge