Sanyo Electric Co., Ltd.

Patrenella Capital Ltd., LLC

Shigeharu Matsushita

Emi Fujii

Yasoo Harada

Hideaki Miyamoto

Kazunari Honma

Satoshi Terada

Daijirou Inoue

Takashi Yamada

Yoh Takano

Minoru Sawada

Naofumi Sakai

Yoshiyuki Ishizuka

Takayoshi Higashino

Akihito Nagamatsu

Takashi Kurose

Kouji Matsumura

Kouichi Yamada

Daijiro Inoue

Yoshiki Murayama

Shigeyuki Murai

Toru Dan

Hisaaki Tominaga

Mitsuaki Harada

Kohji Matsumura

Satoru Sekine

Takeshi Sakai

Tatsurou Gueshi

A memory capable of preventing a memory cell from disappearance of data resulting from accumulated disturbances is obtained. This memory comprises a nonvolatile memory cell and a refresh portion for rewriting data in the memory cell. The refresh portion reads data from and rewrites data in the memory cell in a power-down state.

Memory device configured to refresh memory cells in a power-down state

This memory comprises a bit line, a first word line and a second word line arranged to intersect with the bit line while holding the bit line therebetween and a first ferroelectric film and a second ferroelectric film, having capacitances different from each other, arranged between the bit line and the first word line and between the bit line and the second word line respectively at least on a region where the bit line and the first and second word lines intersect with each other. The bit line, the first word line and the first ferroelectric film constitute a first ferroelectric capacitor while the bit line, the second word line and the second ferroelectric film constitute a second ferroelectric capacitor, and the first ferroelectric capacitor and the second ferroelectric capacitor constitute a memory cell.

Memory

A memory capable of suppressing disturbance causing disappearance of data in a nonselected memory cell is provided. This memory comprises a memory cell array including a bit line, a word line arranged to intersect with the bit line and memory cells connected between the bit line and the word line, for accessing a selected memory cell thereby deteriorating a remanent polarization in an arbitrary memory cell and thereafter performing recovery for recovering all memory cells to remanent polarizations immediately after a write operation or remanent polarizations subjected to single application of a voltage applied to a nonselected memory cell in the access.

This memory comprises a first frequency detecting portion detecting access frequencies with respect to a plurality of memory cell blocks respectively, a comparator comparing the access frequencies with respect to the plurality of memory cell blocks detected by the first frequency detecting portion with each other and a refresh portion exercising control for selecting a prescribed memory cell block from among the plurality of memory cell blocks on the basis of comparison data output from the comparator and preferentially rewriting data in the memory cells included in the selected memory cell block.

Memory with a refresh portion for rewriting data

A memory capable of suppressing reduction of a reading voltage in data reading regardless of dispersion in a manufacturing process is provided. This memory comprises charge storage means, a first field-effect transistor and data determination means. The memory sets a voltage between a control terminal and a remaining first terminal of the first field-effect transistor to a threshold voltage for bringing the first field-effect transistor into an OFF-state in the vicinity of a boundary state between ON- and OFF-states through the threshold voltage of the first field-effect transistor.

A memory allowing reduction of the period of an external access operation is provided. This memory comprises an access control portion performing an internal access operation on the basis of an external access operation, a refresh control portion performing a refresh operation and a refresh division control portion dividing the refresh operation into a read operation RFRD and rewrite operations RFRSand RFRS. The memory performs the read operation RFRD and the rewrite operations RFRSand RFRSat least either before or after different internal access operations corresponding to different external access operations respectively.

A method of fabricating a memory capable of improving the strength of a signal read from a memory cell is provided. This method of fabricating a memory comprises steps of forming a storage part and an etched thin-film part by partially etching a storage material film formed on a first electrode film by a prescribed thickness, forming an insulator film to cover at least the thin-film part of the storage material film and patterning the insulator film and the thin-film part of the storage material film by forming an etching mask on a prescribed region of the insulator film and thereafter etching the insulator film and the thin-film part of the storage material film through the etching mask.

Method of fabricating memory and memory

A dielectric device having excellent characteristics is provided. This dielectric device comprises such a first electrode layer that constituent elements located on its surface are terminated by halogen atoms and a dielectric film formed on the surface of the first electrode layer terminated by the halogen atoms. When the constituent elements for the first electrode layer located on the surface thereof are terminated by the halogen atoms in order to form a ferroelectric film having a bismuth layer structure, therefore, Bi constituting the ferroelectric film is inhibited from bonding to the constituent elements located on the surface of the first electrode layer.

Dielectric device having dielectric film terminated by halogen atoms

A ferroelectric memory capable of improving disturbance resistance in a non-selected cell by increasing the ratio between voltages applied to ferroelectric capacitors of a selected cell and the non-selected cell respectively is obtained. This ferroelectric memory comprises a bit line, a word line arranged to intersect with the bit line and a memory cell including a switching element arranged between the bit line and the word line and turned on with a threshold voltage having a substantially identical absolute value with respect to either of positive and negative voltage application directions and a ferroelectric capacitor arranged between the bit line and the word line and serially connected to the switching element.

Ferroelectric memory and operating method therefor

A memory includes a first electrode film, a storage material film formed on the first electrode film, provided with a storage part and a thin-film part having a thickness smaller than a thickness of the storage part and which is at least about 15% of the thickness of the storage part on average, a second electrode film formed on the storage part of the storage material film. The thickness of the thin-film part may be between 15% and 95% of the thickness of the storage part. An insulator film may be formed on the thin-film part and the second electrode part, the insulator film formed on the thin-film part having a same pattern as the thin-film part.

Memory device having storage part and thin-film part

A ferroelectric memory capable of improving disturbance resistance in a non-selected memory cell includes a bit line, a word line arranged to intersect with the bit line, and a memory cell, which is arranged between the bit line and the word line an includes a ferroelectric capacitor and a diode serially connected to the ferroelectric capacitor. Thus, when a voltage in a range hardly feeding a current to the diode is applied to a non-selected cell in data writing or data reading, substantially no voltage is applied to the ferroelectric capacitor.

Ferroelectric memory and operating method therefor, and memory device

A ferroelectric memory capable of suppressing false data reading or the like by increasing a read margin is obtained. This ferroelectric memory comprises a circuit applying a read voltage Vto a first electrode and a detector capable of detecting the difference between electric capacitances Cand Cof a ferroelectric film when the potential difference of a second electrode corresponding to the difference between the electric capacitances Cand Cof the ferroelectric film is in excess of a detection limit voltage V. The electric capacitance Cof the second electrode is set to satisfy the following expression:&#xd7;{()&#x2212;()}.

Ferroelectric memory

A semiconductor memory device having a first memory including a bit line, a word line arranged to intersect with the bit line and a storage unit arranged between the bit line and the word line, and a second memory different in type from the first memory. The first memory and the second memory are formed on a semiconductor substrate in a stacked manner reducing the thickness in the height direction and attaining further miniaturization (thinning). Further, no wire having a large parasitic capacitance or solder is employed for connecting the first memory and the second memory, thereby enabling high-speed data transfer between the first memory and the second memory.

Semiconductor memory device

A dielectric element capable of effectively suppressing diffusion of oxygen into a region located under a lower electrode in heat treatment for sintering an oxide-based dielectric film is obtained. This dielectric element comprises a lower electrode including a first conductor film having a function of suppressing diffusion of oxygen, a first dielectric film, formed on the lower electrode, including an oxide-based dielectric film, and a first insulator film, arranged on a region other than the lower electrode, having a function of suppressing diffusion of oxygen. Thus, the first conductor film and the first insulator film function as barrier films preventing diffusion of oxygen, whereby the first conductor film effectively prevents oxygen from diffusing downward along grain boundaries of the lower electrode while the first insulator film effectively prevents oxygen from diffusing downward from the region other than the lower electrode in heat treatment for sintering the oxide-based dielectric film.

Dielectric element including oxide-based dielectric film and method of fabricating the same

A memory device capable of improving the degree of integration and effectively preventing false data reading is obtained. This memory device comprises a pair of bit lines extending in a prescribed direction, a word line arranged to intersect with the pair of bit lines and a memory cell, arranged between the pair of bit lines and the word line, consisting of two capacitance elements. Thus, the area of the memory cell is reduced and no reference voltage is required.

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Katano, Japan

Shigeharu Matsushita