Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Shigefumi Irieda

Yasuhiro Shiino

Eietsu Takahashi

Kenri Nakai

Daisuke Kouno

Koki Ueno

Tokumasa Hara

Masashi Yoshida

Tomoaki Nakano

Kiichi Tachi

Susumu Tamon

Manabu Sakaniwa

Hironori Uchikawa

Osamu Torii

Akira Yamaga

Kejen Lin

Juan Shi

According to one embodiment, a controller writes either processed data or preprocessing data and flags into each page included in m pages. The processed data is data after first data translation of write data to be written into a relevant page. The preprocessing data is data before the first data translation of the write data to be written into the relevant page. Each of the flag at least represents whether or not the first data translation is performed for write data to be written into the relevant page.

Memory system

According to one embodiment, a memory device includes a plurality of memory cells; and a first word line connected to the memory cells. When data is written, a first program voltage is applied to the first word line, a first verify voltage is applied to the first word line to obtain a first verify result, a second program voltage is applied to the first word line, a second verify voltage is applied to the first word line to obtain a second verify result, and among the memory cells, a first memory cell whose first verify result is a pass is set to a program inhibited state when the second program voltage is applied and set as a target of the detection of the second verify result.

Programming and verification methods for three-dimensional memory device

For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.

Non-volatile semiconductor storage device

A controller executes a first data conversion for write data to be written into a first page. The first data conversion includes increasing a ratio of a number of a first value to a total number of pieces of data. The controller executes a second data conversion for write data to be written into a second page. The second data conversion includes increasing a ratio of the number of the second value to the total number of pieces of data.

Memory system and method of controlling nonvolatile memory by converting write data written to a page

According to one embodiment, a semiconductor memory device includes a first memory cell, a second memory cell, and a third memory cell, a first word line coupled to the first memory cell, the second memory cell, and the third memory cell, a first bit line coupled to the first memory cell, a second bit line coupled to the second memory cell, and a third bit line coupled to the third memory cell. A first voltage, a second voltage, and a third voltage are sequentially applied to the first word line, and a fourth voltage is applied to the first bit line when the first voltage is applied to the first word line, applied to the second bit line when the second voltage is applied to the first word line, and applied to the third bit line when the third voltage is applied to the first word line.

Semiconductor memory device

A non-volatile semiconductor memory device according to one embodiment includes: a cell array; and a data writing unit that repeatedly executes a write loop including a programming operation of applying a program voltage to a selected word line and a passage voltage to non-selected word lines during writing of data, in which, when a difference between the passage voltage used in an n-th write loop and the passage voltage used in an n+1-th write loop is expressed as &#x394;Vn and when a condition of L&#x3c;M (L and M are integers) is satisfied, the data writing unit executes the write loop using the passage voltage where &#x394;V(L&#x2212;1)&#x3c;&#x394;VL, &#x394;VL&#x2266;&#x394;V(M&#x2212;1), and &#x394;V(M&#x2212;1)&#x3c;&#x394;VM.

Nonvolatile semiconductor memory device

A semiconductor storage device has a plurality of memory cells each having a control gate that are formed on a well. The semiconductor storage device has a control circuit that applies a voltage to the well and the control gates. In an erase operation of the memory cell, the control circuit applies a first pulse wave of a first erasure voltage that rises stepwise to the well and then applies a second pulse wave of a second erasure voltage to the well.

Semiconductor storage device

A nonvolatile semiconductor memory device in accordance with an embodiment includes: a memory cell array having electrically rewritable nonvolatile memory cells; and a control unit. The control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write verify operation being an operation to verify whether data write is completed or not, and the step-up operation being an operation to raise the write pulse voltage if data write is not completed. The control unit, during the write operation, raises a first write pulse voltage with a first gradient, and then raises a second write pulse voltage with a second gradient, thereby executing the write operation, the first write pulse voltage including at least a write pulse voltage generated at first, the second write pulse voltage being generated after the first write pulse voltage, and the second gradient being larger than the first gradient.

Nonvolatile semiconductor memory device using write pulses with different voltage gradients

A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation. The control unit is configured to perform a soft-programming operation of setting the memory cells from an over-erased state to a first threshold voltage distribution state when, in a series of erase operations, the number of erase voltage applications is more than a first number and less than a second number (the first number&#x3c;the second number). The control unit is configured not to perform the soft-programming operation when the number of erase voltage applications is equal to or less than the first number or equal to or more than the second number.

Growing community of inventors

Yokohama, Japan

Shigefumi Irieda