Fujitsu Corporation

Shigeatsu Samukawa

Jun Tanaka

Hiroyuki Sato

Junichi Tamura

Tomohiro Shinomiya

Akihiro Yasuo

Jinichi Yoshizawa

Noriyuki Suzuki

Hirotomo Miyawaki

Masahiro Shirai

Naomi Ikeda

Nobuyuki Umeda

Disclosed is a ring network in which a plurality of transmitting apparatuses are connected in ring form so as to be capable of transmitting in each of upstream and downstream directions, working and protection channels are assigned to each direction and, when failure occurs in a transmission path, a transmit signal is looped back using the protection channel to effect rescue. The ring network includes an insert transmitting apparatus that incorporates a packet, which enters from a lower-order side, into a higher-order signal and transmits the signal to a transmission path, and a drop transmitting apparatus that extracts the packet from the higher-order signal and transmits the packet to another lower-order side. Monitoring is performed to determine whether communication between the insert and drop transmitting apparatus has become unrescuable owing to transmission-path failure. When communication has become unrescuable, the insert transmitting apparatus halts the transmission of the packet to the transmission path.

Transmitting apparatus

A terminating apparatus for an ATM adaptation layer is made of hardware logic circuits to terminate received cells connection by connection and assemble an ATM adaptation layer message for each connection from data contained in the received cells. The apparatus is compact and operates at high speed. The structure of the apparatus is independent of the number of connections to terminate. The apparatus has a-header extractor ( - ) for extracting a virtual path indication/virtual channel indication (VPI/VCI) from a received cell, a CRC unit ( - ) shared by cells of different connections, a reception processor ( - ) for determining whether or not the received cell is the last cell of an ATM adaptation layer message according to a payload type indication (PTI) contained in a header of the received cell and processing the received cell, a work memory ( - ) for storing, for each connection, a CRC result and the number of received cells, and a reception buffer ( - ) for sequentially storing, for each connection, data contained in cells received for the connection.

Terminating apparatus for ATM adaptation layer

An elastic memory determines an amount of delay of input data relative to other input data according to a phase difference between synchronous pulses each indicating a header of a frame of the associated input data. The elastic memory thus synchronizes both input data in the channel level. Both input data are time-division multiplied by a first multiplier. On the other hand, each counter receives synchronous pulses and thereby counting up to make a ROM produce address value of which order is determined previously according to the counted value. These address values are multiplied by a second multiplier. A decoder controls a RAM, a high-impedance control unit and a flip-flop to write in and read out of the RAM the input data. The read data are divided by a signal restoring device.

Memory control device

Growing community of inventors

Kawasaki, Japan

Shigeatsu Samukawa