Sharp Kabushiki Kaisha Corporation

Shige Furuta

Yuhichiroh Murakami

Yasushi Sasaki

Seijirou Gyouten

Makoto Yokoyama

Takahiro Yamaguchi

Shuji Nishi

Etsuo Yamamoto

Hidekazu Yamanaka

Hiroyuki Ohkawa

Hiroyuki Adachi

Shinsaku Shimizu

Kohei Hosoyachi

Keiichi Ina

Yohsuke Fujikawa

Yasuyoshi Kaise

Junichi Yamada

Satoshi Fujii

Takuya Hachida

Nami Nagira

A layout pattern of a demultiplexer circuit of a display device employing the SSD method is configured as described below. Specifically, demultiplexers in the demultiplexer circuit are grouped with three demultiplexers as one set, and nine transistors as switching elements included in the three demultiplexers of each set are arranged to be aligned in the extending direction of a source line with three transistors as a unit while positions of the nine transistors are sequentially shifted in the vertical direction with respect to the source line. Furthermore, any two adjacent sets are arranged such that a direction in which nine transistors included in one set are shifted in the vertical direction with three transistors as a unit and a direction in which nine transistors in the other set are shifted in the above-described vertical direction with three transistors as a unit are opposite to each other.

Active matrix substrate and display device including the same

A display device includes a pixel unit, a binary driver, and a timing generator. The display device is an active matrix display device configured to receive a data signal including image data and other data different from the image data. The pixel unit includes a memory configured to store the image data. The binary driver includes a first holding circuit configured to hold the image data and at least one second holding circuit configured to hold the other data. The timing generator is configured to generate a drive signal used for driving the binary driver.

Display device using binary driver having several holding circuits

A plurality of pieces of serial data are supplied to a liquid crystal display device from an outside. An SI signal selection circuit switches processing target data to be captured between one piece of serial data included in the plurality of pieces of serial data and the plurality of pieces of serial data in accordance with a serial data selection signal. The processing target data captured by the SI signal selection circuit is converted into parallel data by a data conversion circuit. In accordance with one clock pulse of a serial clock, serial-parallel conversion processing is performed in parallel on a plurality pieces of serial data.

Liquid crystal display device

The display device includes, on a substrate, a plurality of pixel electrodes, M (M is a natural number equal to or greater than three) counter electrodes disposed opposite the plurality of pixel electrodes, M counter electrode wiring lines connected with M counter electrodes, and N (N is a natural number and 2&#x2264;N&#x3c;M) common voltage wiring lines connected to the M counter electrode wiring lines. Counter electrode wiring lines connected to counter electrodes adjacent to each other are connected to common voltage wiring lines that are different from each other.

Display device

A data signal line drive circuit includes: a shift register including a plurality of unit circuits; a first latch portion including a plurality of first latch circuits; and a second latch portion including a plurality of second latch circuits. Here, the k-th (k is a natural number) second latch circuit is provided with first latch signals provided to (k+1)-th and subsequent first latch circuits as a second latch signal, so that the capturing of data signals at the second latch portion is split into two or more timings.

Data signal line drive circuit and liquid crystal display device provided with same

A decline in the display quality in portion areas corresponding to source lines that run through an inner non-display area in a display area is reduced. The arrangement of source lines that run through an inner non-display area is changed in an upper change area and a lower change area so that the source lines that are simultaneously driven are not adjacent to each other in a display area and are adjacent to each other in a passage area.

Active matrix substrate and display device

An active matrix substrate includes pixel lines disposed in a display area and connected to pixels, respectively, a signal input section for inputting a signal to the pixel lines, and connection lines connected to the signal input section and the pixel lines. The pixel lines include a short pixel line having a smaller line length than other pixel lines. The connection lines include a short pixel connection line connected to the short pixel line and other connection lines connected to the other pixel lines, one connection line of the short pixel connection line and the other connection lines includes a line resistance adjusting section that adjusts a line resistance of the one connection line according to an electric resistance of the pixel line connected to the one connection line.

Active matrix substrate and display panel

Provided is a shift register circuit capable of preventing occurrence of malfunction caused by a threshold shift of a thin-film transistor due to an influence of external light. A unit circuit constituting each stage of the shift register circuit includes a plurality of thin-film transistors. The plurality of thin-film transistors are categorized into a first group (T, T, T) whose on-off state is controlled at relatively high on-duty and a second group (T, T, T, T, T, T) whose on-off state is controlled at relatively low on-duty. In such a configuration, a light shielding film (LS) is provided only for the thin-film transistor included in one of the first group and the second group.

Shift register circuit

A unit circuitof a shift register is provided with a transistor Trfor supplying an off potential to a node nvia a drain terminal when performing an all-on output. An all-on control signal AON is supplied to a gate terminal of the transistor Tr. Instead of a low level potential VSS supplied from a power supply circuit, an initialization signal INIT which becomes a low level when performing the all-on output supplied to a source terminal of the transistor Tr. Since the all-on signal AON and the initialization signal INIT are supplied from an outside, even if noise is imposed on the low level potential VSS when performing the normal operation, the transistor Trdoes not turn on and charge does not escape from the node. With this, it is possible to prevent malfunction of the shift register due to noise imposed on the off potential supplied from the power supply circuit.

Shift register

A unit circuitof a shift register is provided with a transistor Trhaving a drain terminal connected to a node N, a source terminal to which an off potential is applied, and a gate terminal connected to an output terminal OUT, in order to stabilize a potential of the node N. The unit circuitis further provided with a transistor Trhaving a drain terminal connected to the output terminal OUT, a source terminal to which the off potential is applied, and a gate terminal to which an initialization signal INIT is supplied. With this, when performing an initialization, it is possible to control the potential of the node Nto be a desired level and initialize the shift register certainly, irrespective of a state of the transistor Trbefore the initialization.

An object of the present invention is to realize a display device having a layered wiring structure, that is capable of detecting leakage without fail by using a simple testing circuit. Source bus lines (SL) are wired such that, in the layered region, two source bus lines (SL) adjacent in a vertical direction are a combination of a source bus line (SL) of an odd-numbered column and a source bus line (SL) of an even-numbered column, and two source bus lines (SL) adjacent in a horizontal direction are a combination of a source bus line (SL) of an odd-numbered column and a source bus line (SL) of an even-numbered column. Potentials of different magnitudes are supplied respectively to source bus lines (SL) of odd-numbered columns and source bus lines (SL) of even-numbered columns via testing lines.

In a display device having a layered wiring structure of P layers, and employing a Q-column reversal driving method in which a polarity of a video signal is reversed every Q source bus lines, the plurality of source bus lines are wired to the plurality of layers such that taking source bus lines of a number equal to a double of a least common multiple of P and Q as one group, the number of source bus lines to which positive video signals are applied matches the number of source bus lines to which negative video signals are applied in each of the layers in each of horizontal scanning periods.

Display device with layered wiring structure for external connection

A shift register according to the present invention is a shift register in which a plurality of unit circuits are connected in cascade, wherein the unit circuit includes a first output transistor whose current path is connected between an output terminal and a clock terminal to which a first clock signal is provided; a second output transistor whose current path is connected between the output terminal and a predetermined potential node; a setting device which, when a control signal is active, sets a signal level of the output terminal to a predetermined signal level; a first output control device which provides a signal level of the control signal to a control electrode of the first output transistor to turn off the first output transistor when the control signal is active; and a second output control device which turns off the second output transistor when the control signal is active.

Shift register and display apparatus

A shift register is configured by connecting unit circuitsin multiple stages. An output transistor Trswitches between whether or not to output a clock signal CKA in accordance with a gate potential. A set transistor Trswitches between whether or not to provide an output of an on-potential output unitto a gate terminal of Trin accordance with an output of a set control unit. The set control unitcontrols a gate terminal of Trinto a floating state in part of a period during which a high-level potential is provided to the gate terminal of Tr. The gate potential of Tris raised by being pushed up, whereby a high-level potential without a threshold drop is provided to the gate terminal of Tr, and rounding of an output signal OUT is decreased when the output signal OUT shifts to a high level. Accordingly, an operation margin with respect to fluctuation of a threshold voltage of the transistor is increased.

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Osaka, Japan

Shige Furuta