Taiwan Semiconductor Manufacturing Comp. Ltd.

Shien-Yang Wu

Sun-Jay Chang

Wei-Chang Kung

Jhon Jhy Liaw

Min-Chang Liang

Shi-Bai Chen

Kuo-Hua Pan

Ta-Chun Lin

Chia-Hsin Hu

Chung-Shi Liu

Kong-Beng Thei

Wen-Hsing Hsieh

Ching-Fang Huang

Yung-Shun Chen

Chung Long Cheng

Hsueh-Shih Fan

Harry-Hak-Lay Chuang

Hung-Der Su

Yuan-Hung Chiu

Jye-Yen Cheng

Tseng Chin Lo

Chuan-Yi Lin

Tung-Heng Shie

Wei-Chan Kung

Yee-Chia Yeo

Jhon-Jhy Liaw

Harry Chuang

Wen-Chin Lee

Ta-Lee Yu

Jyh-Huei Chen

Ju-Wang Hsu

Yi-Chun Huang

Hung Der Su

Minchang Liang

Kuo-Tsai Li

Kuan-Yao Wang

Konrad Young

A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.

Gate-all-around (GAA) method and devices

A semiconductor device includes a substrate having a first region and a second region. Multiple nanostructures are vertically stacked above the first region of the substrate. A first gate dielectric layer wraps each of the nanostructures. A first gate electrode layer is disposed on the first gate dielectric layer. A fin protruding from the second region of the substrate. The fin includes alternating first and second semiconductor layers with different material compositions. A second gate dielectric layer is disposed on top and sidewall surfaces of the fin. A second gate electrode layer is disposed on the second gate dielectric layer. A thickness of the first gate dielectric layer is smaller than a thickness of the second gate dielectric layer.

Semiconductor devices having gate dielectric layers of varying thicknesses and methods of forming the same

Various fuse structures are disclosed herein that exhibit improved performance, such as reduced electro-migration. An exemplary fuse structure includes an anode, a cathode, and a fuse link extending between the anode and the cathode. A plurality of anode contacts are coupled to the anode, and a plurality of cathode contacts are coupled to the cathode. The plurality of cathode contacts are arranged symmetrically with respect to a centerline of the fuse link.

Electrical fuse structure and method of formation

A method includes forming a first channel region, a second channel region, and a third channel region over a substrate, depositing a first interfacial layer over the first, second, and third channel regions, removing the first interfacial layer from the first and second channel regions, depositing a second interfacial layer over the first and second channel regions, thinning a thickness of the second interfacial layer over the first channel region, depositing a high-k dielectric layer over the first, second, and third channel regions, and forming a gate electrode layer over the first, second, and third channel regions.

An exemplary method includes forming a fuse structure and forming a first cathode connector and a second cathode connector over the fuse structure. The fuse structure includes an anode, a cathode, and a fuse link extending between and connecting the anode and the cathode. The fuse link has a width defined between a first edge and a second edge, which extend a length of the fuse link. The cathode includes a central region defined by a first longitudinal axis and a second longitudinal axis extending respectively from the first edge and the second edge. The first cathode connector and the second cathode connector are equidistant respectively to the fuse link, the first cathode connector does not intersect the first longitudinal axis, and the second cathode connector does not intersect the second longitudinal axis, such that the central region is free of the first cathode connector and the second cathode connector.

A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

A method of generating a layout usable for fabricating an integrated circuit is disclosed. The method includes generating a block layout layer usable in conjunction with a first conductive layout layer. The first conductive layout layer includes a fuse layout pattern, and the block layout layer includes a block layout pattern overlapping a portion of a fuse line portion of the fuse layout pattern. A second conductive layout layer is generated to replace the first conductive layout layer. The generating the second conductive layout layer includes performing an optical proximity correction (OPC) process on the first conductive layout layer except the portion of the fuse line portion of the fuse layout pattern corresponding to the block layout pattern.

Method and system of generating layout

A structure includes a word-line, a bit-line, and an anti-fuse cell. The anti-fuse cell includes a reading device, which includes a first gate electrode connected to the word-line, a first gate dielectric underlying the first gate electrode, a drain region connected to the bit-line, and a source region. The first gate dielectric has a first thickness. The drain region and the source region are on opposite sides of the first gate electrode. The anti-fuse cell further includes a programming device including a second gate electrode connected to the word-line, and a second gate dielectric underlying the second gate electrode. The second gate dielectric has a second thickness smaller than the first thickness. The programming device further includes a source/drain region connected to the source region of the reading device.

Anti-fuse cell structure including reading and programming devices with different gate dielectric thickness

Method and system of generating a layout including a fuse layout pattern

A fuse device and method for fabricating the fuse device is disclosed. An exemplary fuse device includes a first contact and a second contact coupled with a metal-semiconductor alloy layer, wherein the metal-semiconductor alloy layer extends continuously between the first contact and the second contact. The metal-semiconductor alloy layer is disposed over an epitaxial layer that is disposed over a fin structure of a substrate.

Fin-like field effect transistor (FinFET) based, metal-semiconductor alloy fuse device and method of manufacturing same

An embodiment is a fuse structure. In accordance with an embodiment, a fuse structure comprises an anode, a cathode, a fuse link interposed between the anode and the cathode, and cathode connectors coupled to the cathode. The cathode connectors are each equivalent to or larger than about two times a minimum feature size of a contact that couples to an active device.

A method of forming a Bipolar Junction Transistor (BJT) includes forming an elongated collector line, forming an elongated emitter line parallel to the collector line, and forming an elongated base line parallel to the collector line and positioned between the collector line and the base line. The emitter line, the base line, and the collector line are formed over fin structures.

Bipolar junction transistor formed on fin structures

Growing community of inventors

Jhudong Town, Taiwan

Shien-Yang Wu