Xilinx, Inc.

Shidong Zhou

Santosh Yachareni

Jing Jing Chen

Sree Rkc Saraswatula

Narendra Kumar Pulipati

Anil Kumar Kandala

Michael Tsivyan

Brian C Gaide

Weiguang Lu

Karthy Rajasekharan

Sandeep Vundavalli

Steven P Young

David P Schultz

Nui Chong

Gubo Huang

Mehul R Vashi

Philip D Costello

James D Wesselkamper

Sundeep Ram Gopal Agarwal

Koushik De

Robert I Fu

Vikram Santurkar

Teja Masina

Sree R K C Saraswatula

Sourabh Goyal

Vishwak R Manda

Yi-hui Hsieh

Abhimanyu Kumar

First and second sensing circuits are coupled to first and second data lines, respectively, and sense levels of current leakage or a memory cell state on the first and second data lines. First and second keeper circuits are coupled to the first and second data lines, respectively, and drive the first and second data lines by a voltage supply through biased transistors. First and second leakage latches are coupled to receive and latch state of signals output from the first and second sensing circuits, respectively. A control circuit is coupled to the first leakage latch, second leakage latch, and outputs of the first and second sensing circuits. The control circuit is configured to select either the signal output from the first sensing circuit or the signal output from the second sensing circuit in response to states of the first and second leakage latches.

Current leakage management controller for reading from memory cells

Some examples described herein relate to multi-chip devices. In an example, a multi-chip device includes first and second chips. The first chip includes a power supply circuit and a logic circuit. The first and second chips are coupled together. The second chip is configured to receive power from the power supply circuit. The second chip includes a programmable circuit, a pull-up circuit, and a detector circuit. The detector circuit is configured to detect a presence of a power voltage on the second chip and responsively output a presence signal. The power voltage on the second chip is based on the power from the power supply circuit. The logic circuit is configured to generate a pull-up signal based on the presence signal. The pull-up circuit is configured to receive the pull-up signal and configured to pull up a voltage of a node of the programmable circuit responsive to the pull-up signal.

Multi-chip devices

An example configuration system for a programmable device includes: a configuration memory read/write unit configured to receive configuration data for storage in a configuration memory of the programmable device, the configuration memory comprising a plurality of frames; a plurality of configuration memory read/write controllers coupled to the configuration memory read/write unit; a plurality of fabric sub-regions (FSRs) respectively coupled to the plurality of configuration memory read/write controllers, each FSR including a pipeline of memory cells of the configuration memory disposed between buffers and a configuration memory read/write pipeline unit coupled between the pipeline and a next one of the plurality of FSRs.

Programmable device configuration memory system

A device includes an amplifier, a plurality of selector circuitries, and a plurality of fabric dies. The amplifier is configured to output a supply power signal. Each selector circuitry of the plurality of selector circuitries receives the supply power signal from the amplifier. Each fabric die of the plurality of fabric dies has a corresponding selector circuitry of the plurality of selector circuitries. Each selector circuitry corresponding to a die of the plurality of dies is configured to provide the supply power signal received from the amplifier to its corresponding die responsive to a selection signal being asserted. Selector circuitries of the plurality of selector circuitries corresponding to unselected dies of the plurality of dies pull address supply power for the unselected dies to an input other than the supply power signal of the selector circuitries corresponding to the unselected die.

Low offset and enhanced write margin for stacked fabric dies

Examples described herein provide a method for disabling a defective portion of a fabric die of a stacked IC device. The method includes receiving a signal indicating that a portion of a fabric die of a stacked IC device including at least two fabric dies is defective. The method further includes, in response to the signal, pulling a source voltage rail of the defective portion to ground, thereby disabling the portion, and operating the remainder of the fabric die without interference from or contention with the disabled portion. In one example, the stacked IC device is an active on active (AoA) device, and the portion of the fabric die includes a configuration memory cell. In one example, the signal is received after power-up of the stacked IC device.

Yield-centric power gated regulated supply design with programmable leakers

Embodiments herein describe a memory cell (e.g., a SRAM memory cell) that includes power selection logic for disconnecting storage inverters from a reference voltage source when writing data into the cell. In one embodiment, the memory cells may be disposed long distances (e.g., more than 100 microns) from the data drivers in the integrated circuit which can result in the data lines having large RC time constants. In one embodiment, disconnecting the memory cells from a power supply may counter (or mitigate) the large RC time constants of the data lines.

Selectively disconnecting a memory cell from a power supply

Apparatus and associated methods relate to a glitch detection circuit monitoring a duration that a selected fractional supply voltage is below a predetermined voltage threshold. The selected fractional supply voltage may be at the predetermined threshold when the supply voltage is between a valid circuit-supply voltage and a power-on circuit-reset (POR). A glitch detect signal may be generated, for example, when the monitored duration is greater than a predetermined duration threshold. A test glitch generator may generate a test glitch, for example, having selectable voltage and duration, which may be selectably applied to the glitch detection circuit to verify operation. Various exemplary glitch detection circuits may advantageously determine externally produced tampering attempts by detecting circuit-supply voltages and durations that meet specific selectable supply voltage and duration criteria, improving security of sensitive field programmable gate array (FPGA) data by taking protective action in response to the detection.

Glitch detector and test glitch generator

An example read address generation circuit for a static random access memory (SRAM) cell includes an operational amplifier having a non-inverting input coupled to a reference voltage, a memory emulation circuit having an output coupled to an inverting input of the operational amplifier and a control input coupled to an output of the operational amplifier, and a multiplexer having a first input coupled to receive a constant read voltage, a second input coupled to the output of the operational amplifier, and an output coupled to supply a read address voltage to the SRAM cell.

Adaptive read scheme for configuration SRAMs in a programmable device

A circuit for accessing memory elements in an integrated circuit device is described. The circuit comprises a first plurality of memory elements; first line drivers, each of the first line drivers configured to provide a signal to a memory element of the first plurality of memory elements; first line driver buffers configured to control the signals provided by the first line drivers to the first plurality of memory elements; a second plurality of memory elements; second line drivers, each of the second line drivers configured to provide a signal to a memory element of the second plurality of memory elements; second line driver buffers configured to control the signals provided by the second line drivers to the second plurality of memory elements; and wherein one or both of the first line driver buffers and the second line driver buffers are configured to be selectively disabled.

Circuit for and method of accessing memory elements in an integrated circuit device

A circuit for implementing a write operation of a memory is described. The circuit comprises a data line buffer coupled to a data line and an inverted data line for writing data; a plurality of memory elements, each memory element having a first node coupled to the data line and a second node coupled to the inverted data line; and a write assist circuit having a first node coupled to data line and a second node coupled to the inverted data line, wherein the write assist circuit comprises a pair of pull-down transistors comprising first pull-down transistor coupled to the first node of an amplifier portion and a second pull-down transistor coupled to a second node of the amplifier portion, and a pair of pull-up transistors comprising a first pull-up transistor coupled to the first node of the amplifier portion and a second pull-up transistor coupled to the second node of the amplifier portion. A method of implementing a write operation of a memory of a memory is also described.

Circuit for and method of implementing a write operation of a memory

A circuit includes a divider circuit block configured to generate a trim term signal (VBG_TRIM) that is temperature and process independent. The circuit further includes a processing circuit block configured to multiply a temperature dependent reference voltage signal (TAP_GG) by a factor, and to sum the trim term signal with a result of the multiplication to generate an output reference voltage (VGG).

Trimming a temperature dependent voltage reference

An interconnect multiplexer comprises a plurality of CMOS pass gates of a first multiplexer stage coupled to receive data to be output by the interconnect multiplexer; an output inverter coupled to the outputs of the plurality of CMOS pass gates, wherein an output of the output inverter is an output of the interconnect multiplexer; and a plurality of memory elements coupled to the plurality of CMOS pass gates; wherein inputs to the plurality of CMOS pass gates are pulled to a common potential during a startup mode. A method of reducing contention currents in an integrated circuit is also disclosed.

Interconnect multiplexers and methods of reducing contention currents in an interconnect multiplexer

A device for controlling a power-on reset signal can include a constant current source, for controlling a reference current that is independent of a supply voltage, and a trip point detector circuit driven by the reference current. The trip point detector circuit detects when the supply voltage of the device exceeds a first trip point voltage, and de-asserts the power-on reset signal when the supply voltage exceeds the first trip point voltage. The first trip point voltage can be controlled by a sum of a threshold voltage of a first n-type metal-oxide-semiconductor transistor, a voltage drop across a first resistor, and a threshold voltage of a first p-type metal-oxide-semiconductor transistor. The device may further include a hysteresis circuit, for detecting when the supply voltage falls below a second trip point voltage and causing the trip point detector circuit to reassert the power-on reset signal.

Power on-reset with built-in hysteresis

An integrated circuit has an E-fuse sense circuit configured to produce a READ voltage according to a fuse resistance of an E-fuse during a READ operation. The integrated circuit also has a reference sense circuit configured to produce a reference voltage according to a reference resistance of an on-chip reference resistor during the READ operation. The reference sense circuit replicates the E-fuse sense circuit. The E-fuse sense circuit and the reference sense circuit are coupled to a comparator that produces a bit value according to a difference between the READ voltage and the reference voltage.

E-fuse read circuit with dual comparators

In one embodiment, an integrated device is disclosed. For example, in one embodiment of the present invention, a device comprises a logic control, and a combination differential driver coupled to the logic control, wherein the logic control receives a control signal for configuring the combination differential driver as a Low Voltage Differential Signaling (LVDS) driver or as a Transition Minimized Differential Signaling (TMDS) driver.

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Milpitas, CA, United States of America

Shidong Zhou