Arm Limited

University of Michigan

Ecs Partners Limited

Cerfe Labs, Inc.

University of Cyprus

Shidhartha Das

David Michael Bull

James Edward Myers

Mudit Bhargava

Paul Nicholas Whatmough

Glen Arnold Rosendale

Parameshwarappa Anand Kumar Savanth

Emre Ozer

David Theodore Blaauw

Milosch Meriac

George McNeil Lattimore

Hugo John Martin Vincent

Akshay Kumar

Piyush Agarwal

Fernando Garcia Redondo

Bal S Sandhu

Emre Özer

Supreet Jeloka

Xabier Iturbe

Lucian Shifren

Robert Campbell Aitken

Mbou Eyole

Vikas Chandra

Azeez Jennudin Bhavnagarwala

Brian Tracy Cline

Saurabh Pijuskumar Sinha

Pranay Prabhat

Vasileios Tenentes

Matthew Mattina

David Walter Flynn

Balaji Venu

Rahul Mathur

Matthias Lothar Boettcher

John Philip Biggs

Xiaoqing Xu

Subbayya Chowdary Yanamadala

Andreas Hansson

Benoit Labbe

Carl Wayne Vineyard

Paul Darren Hoxey

David Anthony New

Jeremy Patrick Dubeuf

Anand Savanth

Zhiyao Xie

Naveen Suda

Benjamin James Fletcher

Carlos Alberto Paz De Araujo

Wei Wang

Sachin Satish Idgunji

Daniel Kershaw

Andreas Lars Sandberg

Todd Austin

Ganesh Suryanarayan Dasika

Rune Holm

Nikos Nikoleris

David William Howard

Vincent Gouin

Matthew Paul Elwood

Sahan Sajeewa Hiniduma Udugama Gamage

Adeline-Fleur Fleming

Matthew James Walker

Robert Christiaan Schouten

Urmish Ajit Thakker

Yunpeng Cai

Thanusree Achuthan

George Christopher Smart

Tirdad Anthony Takeshian

James Edwards Myers

Chi-Hsiang Huang

Kumara Guru Palaniswamy

Rishav Roy

Ricardo Daniel Queiros Alves

Zacharias Hadjilambrou

Yanos Sazeides

Terrence Sui Tung Mak

Seng Oon Toh

George Mcneil Lattimore

Aspects of the present disclosure relate to an apparatus comprising a plurality of processing elements having a spatial layout, and control circuitry to assign workloads to said plurality of processing elements. The control circuitry is configured to, based on a timing parameter, determine one or more active processing elements to deactivate; determine, based on the spatial layout, one or more inactive processing elements to activate; and deactivate said one or more active processing elements and activate said one or more inactive processing elements.

Methods and apparatus for workload scheduling

Briefly, embodiments, such as methods, systems and/or circuits for controlling a power signal to be supplied to a processing device. In one aspect, a magnitude of a power supplied to a processing device may be changed based, at least in part on an estimated and/or predicted load.

System, method and/or apparatus for controlling a power signal

An integrated circuit device including processing circuitry, communications circuitry configured to provide a communication link with a communication apparatus external to the integrated circuit device, and a memory accessible by the processing circuitry and by the communications circuitry, the memory comprising a memory region to which the processing circuitry has write access and to which the communications circuitry has read access, in which the processing circuitry is configured to write information to the memory region indicative of one or more use conditions of the integrated circuit device, and in which the communications circuitry is configured to access the memory region and to provide the information indicative of the one or more use conditions of the integrated circuit device via the communication link.

Integrated circuit device, system and method

A moderator system that can receive outputs of various stages of the security analytic framework and can receive input from external sources to provide information about emerging styles of attacks. One or more models/behavioral profiles can be curated by the moderator system, and the moderator system can provide updates to components of the security analytics framework.

Moderator system for a security analytics framework

A power meter for measuring power usage in a circuit includes preprocessor and a weighting network. The pre-processor is configured to receive toggle data for a number of power proxy signals in the circuit for a plurality of clock cycles of the circuit in a first time window. The power proxy signals and weighting values are determined automatically from simulated or emulated toggle data. For each power proxy signal, the pre-processor averages the toggle data over one or more clock cycles in one or more second time windows, within the first time window, to provide averaged toggle data, and outputs the averaged toggle data for each second time window. The weighting network is configured to combine the averaged toggle data from the power proxy signals, based on a set of weight values, to provide a measure of the power usage.

Method and apparatus for power measurement in electronic circuit design and analysis

A method and apparatus for performing refactored multiply-and-accumulate operations is provided. A summing array includes a plurality of non-volatile memory elements arranged in columns. Each non-volatile memory element in the summing array is programmed to a high resistance state or a low resistance state based on weights of a neural network. The summing array is configured to generate a summed signal for each column based, at least in part, on a plurality of input signals. A multiplying array is coupled to the summing array, and includes a plurality of non-volatile memory elements. Each non-volatile memory element in the multiplying array is programmed to a different conductance level based on the weights of the neural network. The multiplying array is configured to generate an output signal based, at least in part, on the summed signals from the summing array.

Refactoring mac operations

A non-volatile memory (NVM) crossbar for an artificial neural network (ANN) accelerator is provided. The NVM crossbar includes row signal lines configured to receive input analog voltage signals, multiply-and-accumulate (MAC) column signal lines, a correction column signal line, a MAC cell disposed at each row signal line and MAC column signal line intersection, and a correction cell disposed at each row signal line and correction column signal line intersection. Each MAC cell includes one or more programmable NVM elements programmed to an ANN unipolar weight, and each correction cell includes one or more programmable NVM elements. Each MAC column signal line generates a MAC signal based on the input analog voltage signals and the respective MAC cells, and the correction column signal line generates a correction signal based on the input analog voltage signals and the correction cells. Each MAC signal is corrected based on the correction signal.

Non-volatile memory accelerator for artificial neural networks

A multiply-accumulate method and architecture are disclosed. The architecture includes a plurality of networks of non-volatile memory elements arranged in tiled columns. Logic digitally modulates the equivalent conductance of individual networks among the plurality of networks to map the equivalent conductance of each individual network to a single weight within the neural network. A first partial selection of weights within the neural network is mapped into the equivalent conductances of the networks in the columns to enable the computation of multiply-and-accumulate operations by mixed-signal computation. The logic updates the mappings to select a second partial selection of weights to compute additional multiply-and-accumulate operations and repeats the mapping and computation operations until all computations for the neural network are completed.

Non-volatile memory-based compact mixed-signal multiply-accumulate engine

An integrated circuit includes a first circuit and a power meter coupled to the first circuit at selected proxy locations. The power meter includes circuitry for generating toggle data, such as signal transitions or signal levels, from signals at the proxy locations and combiner circuitry for combining the toggle data in a first time window with a set of weight value to produce a measure of power usage in the first circuit. The proxy locations and weight values are selected automatically based on simulated or emulated signals from a larger set of locations in the first circuit and associated power usage in the first circuit.

Method and apparatus for on-chip power metering using automated selection of signal power proxies

An apparatus and system for remote attestation of a power delivery network is disclosed. Embodiments of the disclosure enable remote attestation of the power delivery network by storing a trusted golden reference waveform in secure memory. The trusted golden reference waveform characterizes a power delivery network in response to a load generated on the power delivery network. A remote cloud server generates a server-generated remote attestation of the power delivery network by receiving an attestation packet from the power delivery network and verifying whether the attestation packet is consistent with an expected power delivery network identity.

Remote attestation of system integrity

Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.

Multi-tier memory architecture

Broadly speaking, the present techniques exploit the properties of correlated electron materials for artificial neural networks and neuromorphic computing. In particular, the present techniques provide apparatuses/devices that comprise at least one correlated electron switch (CES) element and which may be used as, or to form, an artificial neuron or an artificial synapse.

Correlated electron switch elements for brain-based computing

An apparatus and method for detecting a change in electrical properties in a system is disclosed. Embodiments of the disclosure enable the detection of a change in electrical properties in a system by, in response to a load generated on a power delivery network power in at least part of the system, measuring noise induced in the power delivery network in response to the load. Based on the measured noise, a dynamic-response property of the power delivery network is determined and the dynamic-response property is compared to a stored reference dynamic-response property of the power delivery network based on a predetermined load. In the event of a difference between the dynamic-response property and the reference dynamic-response property, a response to the event is triggered to indicate tampering with the power delivery network.

Power rail noise monitoring to detect attempted security tampering or side channel attacks

Various implementations described herein are directed to a device with a voltage-controlled oscillator that receives an enable signal, receives a reset signal, and provides internal pulse signals including one or more coarse internal pulse signals and multiple fine internal pulse signals. The device may have a coarse sampler that receives the one or more coarse internal pulse signal and provides a coarse sampled output signal. The device may have a fine sampler that receives the multiple fine internal pulse signals and provides a fine sampled output signal.

Digital sampling techniques

Analytics processing circuitry can include a data scavenger and a data analyzer coupled to receive the data from the data scavenger. The data scavenger collects data from at least one element of interest of a plurality of elements of interest of an IC. The data analyzer identifies patterns in the data from the data scavenger over a time frame or for a snapshot of time based on a predefined metric. The analytics processing circuitry can further include a moderator and a risk predictor. The risk predictor generates a risk assessment regarding whether the data collected by the data scavenger is indicative of normal behavior or abnormal behavior based at least on the output of the data analyzer and a behavioral model for the IC, which can be device and application specific. A threat response can be performed based on the risk assessment.

Analytics processing circuitry for mitigating attacks against computing systems

Growing community of inventors

Upper Cambourne, United Kingdom

Shidhartha Das