Advanced Micro Devices Corporation

Globalfoundries Inc.

Spansion Llc.

Globalfoundries U.S. Inc.

Cypress Semiconductor Corporation

Hussmann Corporation

Shibly S Ahmed

Bin Yu

Haihong Wang

Cyrus E Tabery

Srikanteswara Dakshina-Murthy

Ming-Ren Lin

Krishnashree Achuthan

Judy Xilin An

Chih-Yuh Yang

Dong-Hyuk Ju

Imran Khan

Chuan Lin

Jun Kang

Zoran Krivokapic

Wiley Eugene Hill

Mahbub Rashed

Suresh Venkatesan

Subramani Kengeri

Jason Eugene Stephens

Dzung T Tran

Yunfei Deng

Irene Y Lin

Hsiao-Han Thio

Yuansheng Ma

Yuan Lei

Matthew S Buynoski

Jongwook Kye

Yider Wu

Roderick Alan Augur

Rod Augur

Deepti A Pant

Jongwook K E

Srikanteswara Dakshina-Murhty

Disclosed is an input buffer with hysteresis-integrated voltage protection devices for avoiding violations of maximum gate-to-source voltage limitations when the maximum input voltage is greater than the maximum gate-to-source voltage limitation. The input buffer includes a chain of transistors including two P-channel FETs (PFETs) and two N-channel FETs (NFETs). The data input to the input buffer controls the gates of the transistors in the chain so the data output from the input buffer at the junction between the PFETs and NFETs is inverted. The input buffer also includes a hysteresis feedback loop to prevent noise-induced switching of the output. The hysteresis feedback loop also includes voltage protection devices integrated therein to avoid maximum gate-to-source violations when the loop results in a hysteresis voltage being fed back into the chain at the source region of a transistor in the chain. Also disclosed is a receiver incorporating the input buffer.

Input buffer with hysteresis-integrated voltage protection devices and receiver incorporating the input buffer

Embodiments of the disclosure provide an input output (IO) structure in which complimentary nodes of a level shifter are utilized to logically block the output of the IO structure from switching until both power supplies to the IO structure are powered up. An illustrative level shifter includes: a cross-coupled pair of PFETs configured to output complimentary voltage values at a first node and a second node; a control circuit configured to select which of the complementary voltage values are output to the first node and second node; a logic inverter having an input coupled to the first node and an output coupled to a third node; and a NAND gate having inputs coupled to the second node and third node and that generates a level shifted output.

Low power power-up reset output driver

A method includes varying spacing between at least one of a source region or a drain region and a well contact region to create a group of configurations. The method further includes determining an effect of latchup on each configuration.

Controlling the latchup effect

An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.

Middle-of-the-line constructs using diffusion contact structures

A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

Junction leakage suppression in memory devices

A double-gate semiconductor device includes a substrate, an insulating layer, a fin and two gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. A first gate is formed on the insulating layer and is adjacent a first sidewall of the fin. The second gate is formed on the insulating layer and is adjacent a second sidewall of the fin opposite the first sidewall. The first and second gates both include a conductive material and are electrically separated by the fin.

Double-gate semiconductor device with gate contacts formed adjacent sidewalls of a fin

A method includes forming a first rectangular mesa from a layer of semiconducting material and forming a first dielectric layer around the first mesa. The method further includes forming a first rectangular mask over a first portion of the first mesa leaving an exposed second portion of the first mesa and etching the exposed second portion of the first mesa to produce a reversed T-shaped fin from the first mesa.

Reversed T-shaped finfet

A method for forming fin structures for a semiconductor device that includes a substrate and a dielectric layer formed on the substrate is provided. The method includes etching the dielectric layer to form a first structure, depositing an amorphous silicon layer over the first structure, and etching the amorphous silicon layer to form second and third fin structures adjacent first and second side surfaces of the first structure. The second and third fin structures may include amorphous silicon material. The method further includes depositing a metal layer on upper surfaces of the second and third fin structures, performing a metal-induced crystallization operation to convert the amorphous silicon material of the second and third fin structures to a crystalline silicon material, and removing the first structure.

Systems and methods for forming multiple fin structures using metal-induced-crystallization

A semiconductor device may include a substrate and an insulating layer formed on the substrate. A fin may be formed on the insulating layer. The fin may include a side surface and a top surface, and the side surface may have a &#x3c;100&#x3e; orientation. A first gate may be formed on the insulating layer proximate to the side surface of the fin.

Formation of semiconductor devices to achieve &#x3c;100&#x3e; channel orientation

Multiple semiconductor devices are formed with different threshold voltages. According to one exemplary implementation, first and second semiconductor devices are formed and doped differently, resulting in different threshold voltages for the first and second semiconductor devices.

Selective channel implantation for forming semiconductor devices with different threshold voltages

A semiconductor device may include a substrate, an insulating layer formed on the substrate and a conductive fin formed on the insulating layer. The conductive fin may include a number of side surfaces and a top surface. The semiconductor device may also include a source region formed on the insulating layer adjacent a first end of the conductive fin and a drain region formed on the insulating layer adjacent a second end of the conductive fin. The semiconductor device may further include a metal gate formed on the insulating layer adjacent the conductive fin in a channel region of the semiconductor device.

Double gate semiconductor device having a metal gate

A fin field effect transistor (FinFET) includes a reversed T-shaped fin. The FinFET further includes source and drain regions formed adjacent the reversed T-shaped fin. The FinFET further includes a dielectric layer formed adjacent surfaces of the fin and a gate formed adjacent the dielectric layer.

Reversed T-shaped FinFET

Growing community of inventors

San Jose, CA, United States of America

Shibly S Ahmed