Huawei Technologies Co., Limited

Shibin Xu

Yongyao Li

Zhongjian Chen

Liangyi Zhang

Nianbing Li

Feng Wang

Fei Luo

Jiang Zhu

Jiankang Li

Wei Kang

Xiaokun Wang

Xue Feng

Kejian Wang

Embodiments of this application disclose a data interface equalization adjustment method and apparatus, a device, and a storage medium, and relate to the field of data interface technologies. The method includes: A second device determines equalization parameter indication information of a first transmitter TX on a first data interface. The second device sends a first equalization training sequence block ETSB to a corresponding RX on the first data interface through a TX on a second data interface, where the first ETSB carries the equalization parameter indication information and equalization target indication information, and the equalization target indication information indicates that the first TX is an equalization target. The first device determines the equalization target to be the first TX based on the equalization target indication information, and adjusts an equalization parameter of the first TX to an equalization parameter indicated by the equalization parameter indication information.

Data interface equalization adjustment method and apparatus, device, and storage medium

This application provides a memory training method, a memory controller, a processor, and an electronic device. The memory controller keeps transmission delays of N DQs unchanged, adjusts a transmission delay of a DQS, and determines a maximum DQS transmission delay and/or a minimum DQS transmission delay of the DQS when all data carried in the N DQs is correctly transmitted. The memory controller adjusts the transmission delay of the DQS to a target DQS transmission delay between the maximum DQS transmission delay and the minimum DQS transmission delay. The method helps quickly align relative timing positions between the DQS and the N DQs. Therefore, memory training may be repeatedly performed in a working process of the processor, so that the N DQs keep long enough timing margins.

Memory training method, memory controller, processor, and electronic device

This application provides an electronic module and an electronic device. The electronic module includes a first component, a second component, and a plurality of terminals. The first component includes a package substrate and a chip mounted on the package substrate. The second component includes a circuit board and a mount base mounted on the circuit board. Each terminal includes a body part, and a first bent part and a solder ball that are respectively connected to two opposite ends of the body part. In each terminal, the body part passes through and is fastened to the mount base, the first bent part presses against a corresponding first solder pad on the package substrate, and the solder ball is connected to a corresponding second solder pad on the circuit board.

Electronic module and electronic device

This application discloses a voltage scaling method and an electronic device. The method is applied to an electronic device having a processor and a power supply that supplies power to the processor. The method includes the processor sending power supply scaling information to the power supply based on an operating frequency in a next time period. The method further includes the power supply determining, based on the power supply scaling information, a supply voltage Vused to supply power to the processor. The supply voltage Vdecreases as a load current of the power supply increases. V≤V≤V, where Vis a lowest supply voltage of the processor at the operating frequency in the next time period, and V is a specified supply voltage of the processor at the operating frequency in the next time period.

Methods and devices for voltage scaling for a processor based on predicted operating frequency

Growing community of inventors

Dongguan, China

Shibin Xu