Skyworks Solutions, Inc.

Texas Instruments Corporation

Shiban Kishan Tiku

Heather L Knoedler

Jiro Yota

Jens Albrecht Riege

Richard S Burton

Viswanathan Ramanathan

Daniel C Weaver

Lam T Luu

Richard S Bingle

Han-Tzong Yuan

Donald L Plumton

Milo R Johnson

Nancy J Gabriel

A semiconductor die includes a substrate layer, one or more metal layers disposed over the substrate layer, and one or more polyimide layers disposed over the substrate. Each polyimide layer can have a trench that separates a first portion of the polyimide layer that is adjacent a metal layer from a second portion of the polyimide layer. The trench(es) can be formed by etching the polyimide layer(s). A topcoat insulation layer can be disposed over the polyimide layers, a portion of the topcoat insulation layer disposed over the trench(es) define a moat. The topcoat insulation layer is impervious to moisture and the moat inhibits moisture from traveling along the one or more polymer interlevel dielectric layers from the second portion to the first portion.

Moisture barrier for metal insulator metal capacitors and integrated circuit having the same

A semiconductor die includes a substrate layer, one or more metal layers disposed over the substrate layer, and a pair of polyimide layers disposed over the substrate so that they define an interface therebetween. One or both of the pair of polyimide layers have a trench that separates the interface from the one or more metal layers. The trench can be formed by etching the polyimide layer(s). A topcoat insulation layer is disposed over the one or more metal layers and polyimide layers. The topcoat insulation layer is impervious to moisture and the trench inhibits migration of moisture along the interface to the one or more metal layers, thereby preventing metal migration from the one or more metal layers along the interface.

Moisture barrier for bond pads and integrated circuit having the same

Method of making moisture barrier for bond pads and integrated circuit having the same

Gate structures for semiconductor devices include a silicon nitride layer, an electron beam evaporated tantalum nitride layer disposed on the silicon nitride layer, a first electron beam evaporated titanium layer disposed on the tantalum nitride layer, an electron beam evaporated gold layer deposited on the first titanium layer, and a second electron beam evaporated titanium layer deposited on the gold layer.

Gate structure with refractory metal barrier

Gate metallization structures and methods for semiconductor devices are disclosed, wherein a refractory metal barrier is implemented to provide performance improvements. Transistor devices are disclosed having a compound semiconductor substrate and an electron-beam evaporated gate structure including a layer of tantalum nitride (TaNx), a layer of titanium (Ti) and a layer of gold (Au).

Refractory metal barrier in semiconductor devices

Apparatus and methods for evaporating metal onto semiconductor wafers are disclosed. One such apparatus can include an evaporation chamber that includes a wafer holder, such as a dome, and a test wafer holder that is separate and spaced apart from the wafer holder. In certain implementations, the test wafer can be coupled to a cross beam supporting at least one shaper. A metal can be evaporated onto production wafers positioned in the wafer holder while metal is evaporated on a test wafer positioned in a test wafer holder. In some instances, the production wafers can be GaAs wafers. The test wafer can be used to make a quality assessment about the production wafers.

Methods of evaporating metal onto a semiconductor wafer in a test wafer holder

Apparatus and methods for uniform metal plating onto a semiconductor wafer, such as GaAs wafer, are disclosed. One such apparatus can include an anode and a showerhead body. The anode can include an anode post and a showerhead anode plate. The showerhead anode plate can include holes sized to dispense a particular plating solution, such as plating solution that includes gold, onto a wafer. The showerhead body can be coupled to the anode post and the showerhead anode plate. The showerhead body can be configured to create a seal sufficient to substantially prevent a reduction of pressure in the plating solution flowing from the anode post to holes of the showerhead anode plate.

Apparatus and methods for uniform metal plating

Apparatus and method for uniform metal plating

Apparatus and methods for evaporation including test wafer holder

According to one embodiment, an NiV adhesion layer is deposited over the backside surface of a semiconductor substrate. The semiconductor substrate might comprise a group III-V compound semiconductor. The NiV adhesion layer can be deposited over the backside surface of the semiconductor substrate in, for example, a magnetron deposition system. In certain embodiments, the backside surface of the semiconductor surface may be cleaned to remove oxides from the surface prior to deposition of the NiV adhesion layer. After the NiV adhesion layer has been deposited, a gold seed layer is deposited over the NiV adhesion layer. Following deposition of the gold seed layer, a second gold layer is electroplated, or otherwise deposited, over the gold seed layer. In one embodiment, the invention is a structure fabricated according to the process steps described above.

Method for metallization of a semiconductor substrate and related structure

Method for metallization of a semiconductor substrate

A method of diffusion of dopants (e.g. zinc) into III-V substrates (e.g. GaAs) using metal silicide and dopants (e.g. W.sub.x Si.sub.y :Zn) is disclosed. A cap layer (e.g. SiO.sub.2 or Si.sub.3 N.sub.4) is also used. The zinc tungsten silicide is formed by cosputtering zinc and tungsten silicide (W.sub.5 Si.sub.3). Applications include adjustment of threshold voltages in JFETs by rapid thermal pulsing of zinc into device channel regions and use of the zinc tungsten silicide as a base contact plus extrinsic base dopant source together with a nitride sidewall self-alignment.

Method for outdiffusion of zinc into III-V substrates using zinc

Thin film resistors formed from a metal silicon nitride film are provided in which tungsten, titanium, tantalum, and other group IV A, V A, and VII A metals are included. The silicon to metal ratio varying between about 0.1 and 10.0 and the nitrogen to metal ratio varying between about 0.1 and 10.0 provide sheet resistances which include the useful range of about 100 to over 10,000 ohms per square for films approximately 2,000 angstroms thick. Deposition of these materials by sputtering a metal silicide target in a nitrogen containing atmosphere, such as 20% nitrogen and 80% argon is also provided.

Thin film resistor and method

Vertical AlGaAs heterojunction bipolar transistors (30) with planar structure together with fabrication methods therefor are disclosed. For an emitter (44) on top structure, the contacts (46) to the base (38) are formed by a diffusion of zinc dopants from the surface, and contacts (42) to the collector (34, 36) are formed by diffusions of sulfur dopants from the surface rather than by etch of connecting vias. Further, device isolation is also provided by zinc diffusions (54) rather than by mesa formation. These diffusions are by rapid thermal pulses.

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Camarillo, CA, United States of America

Shiban Kishan Tiku