Delta Electronics, Inc.

Diodes Inc.

Shiau-Shi Lin

Hsin-Chang Tsai

Tzu-Hsuan Cheng

Chia-Yen Lee

Peng-Hsin Lee

Liang-Cheng Wang

The present invention relates to an electronic component package and a manufacturing method therefor. In an embodiment, the electronic component package comprises: a first metal layer, a high-voltage transistor semiconductor die, a first molding compound layer, a second metal layer, a first vertical connection structure, a second vertical connection structure, a control circuit bare chip, and a second molding compound layer. In the electronic component package of the present invention, a lead frame and electrical leads are replaced with the metal layers and the vertical connection structures, so that the position of the electrical connection of the chip is more flexible and the heat dissipation effect is better. Compared with the lead frames and the electrical leads, the electronic component package of the present disclosure is more suitable for packaging high-voltage or high-current chips.

Electronic component package and manufacuring method thereof

A semiconductor chip package may include a lead frame having a first surface and a second surface opposite to each other. A groove may be provided on the first surface of the lead frame and filled with an adhesive. A semiconductor chip may be disposed over the first groove and affixed on the first surface of the lead frame through the adhesive in the first groove. A carrier may be disposed on the second surface of the lead frame. A method for manufacturing the semiconductor chip package is also provided.

Semiconductor chip package including lead frame and manufacturing method thereof

A package structure includes a substrate, a first capacitor, a System on Chip unit and a wiring layer. The first capacitor is provided on the substrate. The System on Chip unit is bonded with the first capacitor in a first dielectric layer. The wiring layer is configured to electrically couple the first capacitor and the System on Chip unit. The wiring layer is provided on the first dielectric layer through a second dielectric layer.

Package structure and method for fabricating the same

A semiconductor device is provided. The semiconductor device includes a substrate; an active layer disposed on the substrate; a via through the active layer; and a plurality of electrodes disposed on the active layer and into the via. Additionally, a package structure that includes the semiconductor device is also provided. The electrode is electrically connected to the substrate through the via.

Semiconductor devices with via structure and package structures comprising the same

A package structure includes a metal carrier, a conductive adhesive layer disposed on the metal carrier, a conductive post disposed on the conductive adhesive layer, a semiconductor chip disposed on the conductive adhesive layer and laterally spaced from the conductive post, and a redistribution layer disposed on the conductive post and the semiconductor chip. The semiconductor chip includes a first terminal at an upper surface of the semiconductor chip. The first terminal of the semiconductor chip is electrically connected to the bottom surface of the semiconductor chip through the redistribution layer, the conductive post and the conductive adhesive layer.

Package structures and methods for fabricating the same

A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.

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Taoyuan, Taiwan

Shiau-Shi Lin