United Microelectronics Corp.

Novatek Microelectronics Corp.

Shiao-Shien Chen

Tien-Hao Tang

Mu-Chun Wang

Hua-Chou Tseng

Kun-Chih Wang

Mei-Ling Chao

Bing-Chang Wu

Tsun-Lai Hsu

Chen-Chung Hsu

Jih-Wen Chou

Tung-Yang Chen

Shiang Huang-Lu

Chiu-Hsiang Chou

Yu-Shyang Huang

An ESD protection design using a gate-coupled substrate-triggered technique is provided. A required RC time constant maintained in the gate-coupled substrate-triggered ESD circuit is based on a parasitic MOS capacitor and larger resistor, in which a layout area for the substrate-triggered ESD protection design is significantly reduced.

Gate-coupled substrate-triggered ESD protection circuit and integrated circuit therewith

An electrostatic discharge (ESD) protection circuit including a detection circuit for detecting an ESD current and a bypass circuit for bypassing the ESD current is provided. The detection circuit and the bypass circuit are coupled between a first pad and a second pad. The bypass circuit comprises a transistor, a diode, and a resistor. The drain of the transistor is coupled to the first pad. The source of the transistor is coupled to the second pad and a cathode of the diode. The substrate terminal of the transistor is coupled to an anode of the diode and an output terminal of the detection circuit. The resistor is coupled between the substrate terminal and the second pad. The diode keeps the voltage of the substrate terminal sufficient for turning on the transistor.

Electrostatic discharge protection circuit and semiconductor structure for electrostatic discharge

A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor substrate.

Semiconductor chip capable of implementing wire bonding over active circuits

An electrostatic discharge (ESD) protection circuit including a detection circuit for detecting the ESD current and a clamp circuit for bypassing an ESD current between a first pad and a second pad is provided. The detection circuit is connected between the first pad and the second pad, wherein the detection circuit comprises a diode and a variable resistor tuned by a diode, and an output terminal of the detection circuit is connected to the variable resistor. The clamp circuit is connected between the first pad and the second pad and connected to the output terminal of the detection circuit. When the ESD current from the first pad or the second pad is detected by the detection circuit, a trigger voltage is generated to trigger the clamp circuit to bypass the ESD current due to a resistance of the variable resistor is changed by the diode.

Electrostatic discharge protection device and circuit thereof

A structure of an electrostatic discharge protection circuit, in which a buried layer is formed in the substrate of the electrostatic discharge protection circuit, and a sinker layer electrically connected to the buried layer and a drain is also formed therein. Thereby, when the electrostatic discharge protection circuit is activated, the current flows from a source through the buried layer and the sinker layer to the drain. The current flow path is remote from the gate dielectric layer to avoid damaging the gate dielectric by a large current, so as to improve the dielectric strength of the electrostatic discharge protection circuit.

Structure and fabrication method of electrostatic discharge protection circuit

MOS Transistors and bipolar junction transistors are connected to input pads and output pads for implementing electrostatic discharge protection. By conducting a power clamp circuit and applying a substrate-trigger technology, electrostatic discharge protection is further enhanced. For instance, positive ESD stress protection can be enhanced between signal pads (input pads and output pads) and VSS by using NMOS transistors and field oxide devices. Negative ESD stress protection can be enhanced between signal pads and VDD by using PMOS transistors.

Integrated circuit with an electrostatic discharge protection circuit

An electrostatic discharge protection device, including a silicon-control-rectifier, in complementary metal-oxide semiconductor (CMOS) process is disclosed. in one embodiment of the present invention, the protection device includes a semiconductor substrate having a first conductivity type. A well region formed with a second conductivity type in the semiconductor substrate. A first region formed in the well region. A second region formed having a portion in the weil region and another portion outside the well region, but still within the semiconductor substrate. Moreover, a third region formed within the well region and in between the first; region and the second region. A fourth region formed within the semiconductor substrate and outside the well region. A fifth region formed within the semiconductor substrate and in between the second region and the fourth region. Furthermore, the second region and the fifth region form the n-pjunction of a zener diode and the breakdown voltage of the zener diode is controlled by adjusting the ion dosage in the second region.

CMOS silicon-control-rectifier (SCR) structure for electrostatic discharge (ESD) protection

A semiconductor device with substrate-triggered ESD protection has a guard ring, a first MOS transistor array, a second MOS transistor array, a substrate-triggered portion, and an N-well. The first MOS transistor array, the second MOS transistor array, the substrate-triggered portion, and the N-well are formed in a region surrounded by the guard ring, and the substrate-triggered portion is located between the first MOS transistor array and the second MOS transistor array. When the ESD event occurs, the N-well is biased for directing a trigger current.

Layout of semiconductor device with substrate-triggered ESD protection

An electrostatic discharge (ESD) protection circuit formed on a P-type substrate has a first pdiffusion region in the P-type substrate, a N-well in the P-type substrate, a first ndiffusion region in the N-well, a P-well in the N-well, and an n-p-n bipolar junction transistor (BJT) in the P-well. An equivalent circuit between a base and an emitter of the BJT is a diode without connecting to any resistor in parallel.

Substrate-triggered ESD circuit by using triple-well

A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.

A BiCMOS electrostatic discharge (ESD) protecting circuit is triggered by a bipolar junction transistor (BJT) for achieving ESD protection. Due to the layout area of the BJT ESD protecting circuit being smaller than the layout area of an RC circuit, layout area can be reduced. Moreover, the BJT reduces leakage current problems and has a lower triggering voltage. Therefore, the BJT in the ESD protecting circuit can effectively reduce problems of a higher triggering ESD voltage and leakage current.

BiCMOS electrostatic discharge power clamp

A diode structure is provided. The diode structure comprises a first conductive type substrate, a second conductive type first well region, a first conductive type second well region, a second conductive type first doped region, a first conductive type second doped region and a second conductive type third doped region. The first well region is located within the substrate and the second well region is located within the first well region. The first doped region is located within the first well region and detached from the second well region but adjacent to the surface of the substrate. The second doped region and the third doped region are located within the second well region and adjacent to the surface of the substrate. The second doped region is located between the first doped region and the third doped region but detached from both the first doped region and the third doped region.

Diode and diode string structure

An ESD protection device having reduced trigger voltage is disclosed. A first MOS transistor includes a first gate, a first heavily doped region at one side of the first gate, and a second heavily doped region at the other side of the first gate. A second MOS transistor is laterally disposed in proximity to the first MOS transistor. The second MOS transistor includes a second gate, a third heavily doped region at one side of the second gate, and a fourth heavily doped region at the other side of the second gate. The floating gate MOS transistor is located between the first and second MOS transistors. A floating gate MOS transistor is serially connected to the first MOS transistor via the second heavily doped region and is serially connected to the second MOS transistor via the third heavily doped region.

ESD protection device having reduced trigger voltage

A semiconductor device having an electrostatic discharge protective circuitry adapted to a common discharge line (CDL) is disclosed. In the embodiments of the present invention, semiconductor device includes a plurality of bonding pads, each having at least one connecting terminal, a common discharge line, and a protective device connected between the connecting terminal and the common discharge line. Moreover, the protective device is composed of a silicon-control-rectifier that is used for electrostatic discharge protection and a zener diode for lowering a trigger voltage of the silicon-control-rectifier.

Growing community of inventors

Chung-Li, Taiwan

Shiao-Shien Chen