Lucent Technologies Inc.

At&t Bell Laboratories

University of Kentucky Research Foundation

Shianling Wu

Ramesh Karri

Charles Eugene Stroud

James Louis Lewandowski

Victor J Velasco

Miroslaw Guzinski

Concurrent Fault Detector Circuits (CFDCs) are test components of a main system, e.g. an Application Specific Integrated Circuit, and provide the results of the tests in parallel to at least one Error Source Register (ESR). Instead of reading out the ESR in parallel, its contents are copied to a serial shadow register so the contents can be read out in series to an error correcting application, thus reducing the number of output pins and the burden on resources of the main system. The ESR's receipt and transfer of information is under the control of a Boundary Scan Interface. In one embodiment, the test results are prioritized and compared to data in a mask register so that only important errors create a system interrupt which causes the read out of data from the shadow register.

Maintenance registers with Boundary Scan interface

A device (12), such as an A/D converter for generating successive codes, each in accordance with the level of an input analog voltage, may be tested to determine if all codes have been generated by applying a voltage V.sub.t having an amplitude that varies between 0 and V volts. The variation in the voltage V.sub.t is such that when the device (12) is operating properly, it will generate all of its codes during a predetermined interval. Each code generated by the device (12) is compared by a comparator (18) to the count of an n-bit counter (20) whose count is initialized at zero. Each time the count of the counter (20) matches the code produced by the device (12), the counter is incremented. If the counter overflows (i.e., its count has exceeded 2.sup.n -1) within a prescribed interval, then the device (12) is said to be operating properly.

Method and apparatus for all code testing

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Lawrenceville, NJ, United States of America

Shianling Wu