Taiwan Semiconductor Manufacturing Comp. Ltd.

Shiang-Rung Tsai

Chun Hsiung Tsai

Tze-Liang Lee

Tai-Chun Huang

Cheng-Lung Hung

Hsien-Ming Lee

Yi-Hung Lin

Hung-Chin Chung

Hao-Ming Lien

Hsiao-Kuan Wei

Wei-Che Hsieh

Brian Wang

Methods for forming semiconductor structures are disclosed herein. An exemplary method includes forming a gate structure having a dummy gate stack over a substrate, performing a gate replacement process, such that the dummy gate stack is replaced with a metal gate stack, and forming a non-silane based oxide capping layer over the gate structure. The gate replacement process includes removing a portion of the dummy gate stack from the gate structure, thereby forming a gate trench. A work function layer is formed in the gate trench, a blocking layer is formed in the gate trench over the work function layer, and a metal layer (including, for example, aluminum) is formed in the gate trench over the blocking layer. The blocking layer includes titanium and nitrogen with a titanium to nitrogen ratio that is greater than one. In some implementations, the work function layer is formed over a dielectric layer.

Metal gate structure with multi-layer composition

An injector for forming films respectively on a stack of wafers is provided. The injector includes a plurality of hole structures. Every adjacent two of the wafers have therebetween a wafer spacing, and each of the wafers has a working surface. The hole structures respectively correspond to the respective wafer spacings. The working surface and a respective hole structure have therebetween a parallel distance. The parallel distance is larger than a half of the wafer spacing. A wafer processing apparatus and a method for forming films respectively on a stack of wafers are also provided.

Injector for forming films respectively on a stack of wafers

The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate and a gate stack disposed on the semiconductor substrate. The gate stack includes a high-k dielectric material layer, a titanium-rich TiN layer over the high-k dielectric layer, and a metal layer disposed over the titanium-rich TiN layer. The metal layer includes aluminum.

An embodiment method of controlling fin bending in a fin field-effect transistor (FinFET) includes forming an isolation region over a substrate, performing a first annealing process, the first annealing process including a first wet anneal, a second wet anneal, and a first dry anneal. In an embodiment, the first annealing process is followed by a chemical mechanical planarization (CMP) process, an etching process, and a second annealing process for the isolation region.

FinFET fin bending reduction

An embodiment method of controlling fin bending in a fin field-effect transistor (FinFET) includes forming an isolation region over a substrate, performing a first annealing process, the first annealing process including a first wet anneal, the first wet anneal removing impurities from the isolation region; a second wet anneal, the second wet anneal forming silanol in the isolation region; and a first dry anneal, the first dry anneal dehydrating the isolation region. In an embodiment, the first annealing process is followed by a chemical mechanical planarization (CMP) process, an etching process, and a second annealing process for the isolation region.

The present disclosure relates a method to mitigate wafer warpage in advanced technology manufacturing processes due to crystallization of one or more amorphous layers with asymmetrical front-surface and back-surface layer thicknesses. After deposition of one or more layers of amorphous material on a front-surface and a back-surface of the wafer in a furnace tool, the front-surface layers are patterned which thins a front layer thickness. Downstream thermal processing performed at a temperature which exceeds a crystallization threshold of the amorphous material will result in asymmetric stress between the front and back surfaces due to the asymmetrical layer thicknesses. To mitigate this effect, the amount of warpage as a function of the difference in asymmetrical layer thickness may be determined such that a front-surface deposition tool may be utilized in conjunction with the furnace tool to reduce the difference in front-surface and back-surface layer thicknesses. Other methods are also disclosed.

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Hsinchu, Taiwan

Shiang-Rung Tsai