United Microelectronics Corp.

Shiang Huang-Lu

Mu-Chun Wang

Tien-Hao Tang

Kuan-Yu Fu

Tzung-Han Lee

Shiao-Shien Chen

Kun-Cho Chen

Shih-Chieh Kao

Yuan-Chang Liu

Chau-neng Wu

A via plug layout structure for connecting different metallic layers. The structure includes a plurality of via plugs arranged in a fan-shaped pattern and a plurality of empty bars positioned between a single via plug and the fanned-out via plugs so that incoming current to the single via plug is equally distributed to every one of the fanned-out via plug and current stress in each fanned-out via plug is identical. Hence, via plugs having particularly serious electromigration problem can be discovered. In addition, single via plug having different critical dimension can be fabricated so that maximum critical dimension sustainable by the via plug is determined after an electromigration test.

Via plug layout structure for connecting different metallic layers

A electrostatic discharge (ESD) device with salicide layers isolated by a shallow trench isolation in order to save one salicide block photomask. A shallow trench isolation is formed in drain region to isolate a portion of the drain region, so that the drain region is partitioned into two parts. A salicide layer is formed on the drain region. Since the salicide layer is not formed on the shallow trench isolation, without using an additional photomask, the salicide layer on the drain region is partitioned into two parts. The effect of the local thermal energy occurring to drain junction upon the contact metal of the drain region is eliminated.

ESD device with salicide layer isolated by shallow trench isolation for saving one salicide block photomask

A method for protecting the gate oxide layer of a MOS device. The method can also be used to monitor the intensity of radiation and charged particles falling on the gate oxide layer. The method includes the provision of a substrate having a gate structure thereon and an inter-layer dielectric layer over the gate structure, wherein the gate structure further includes a gate oxide layer and a gate electrode. Thereafter, a shielding layer is formed over the inter-layer dielectric layer, and then a protection diode is formed to link the shielding to the substrate.

Method for protecting gate oxide layer and monitoring damage

A method of protecting a well at a floating stage. In a first conductive type substrate, a second conductive type well is formed. A first conductive type heavily doped region and a second conductive type heavily doped region are respectively formed in the first conductive type substrate and the second conductive type well. These two heavily doped regions are electrically connected with each at an early stage of fabrication process to provide a protection from being damaged during subsequent plasma process or other processes. While forming a top metal layer of a multi-level interconnect, these two heavily doped regions are disconnected, that is, open to each other, to obtain a better electrical characteristic of the device or the integrated circuit formed on the substrate.

Method of protecting a well at a floating stage

A circuit for evaluating the asymmetric antenna effect of a transistor pair is provided, which can be implemented by using bipolar or complementary metal oxide semiconductor (CMOS) transistors to implement a differential amplifier, with which a pair of transistors Q,and Q,having similar characteristics are connected. The transistors Q,and Q,have a structure of, for example, one polysilicon layer and three metal layers, in which a second metal layer M,and a third metal layer M,are used for signal input, and metal layer M,close to the gate oxide layer of both the transistors Q,and Q,are used to obtain a differential antenna ratio. The differential amplifier comprises transistors Q,and Q,serving as an active load, and transistor Q,, which is used for adjusting the voltage gain.

Circuit for evaluating an asysmetric antenna effect

A wafer acceptance testing (WAT) method with a test key is provided. The test key structure includes a testing structure on a substrate. An inter-layer-dielectric layer covers over the substrate to isolate the testing structure. A grounded metal layer is located on the inter-layer dielectric layer. An interconnecting structure is located on the grounded metal layer. A conductive pad layer and a passivation layer are sequentially located on the interconnecting structure. The testing structure is electrically coupled to the interconnecting structure. The interconnecting structure is also electrically coupled to the conductive pad layer. The grounded metal layer is grounded without any further coupling such that the grounded metal layer is not coupled to the testing structure and the interconnecting structure.

Wafer acceptance testing method and structure of a test key used in the method

A method for preventing horizontal and vertical crosstalk between conductive layers forms a dummy conductive layer between conductive layers and between conductive lines within a dielectric layer. The dummy conductive layer does not connect with conductive layers or conductive lines. Because the dummy conductive layer has a shielding effect for conductive layers, the method can reduce the horizontal and vertical crosstalk between conductive layers.

Method for preventing crosstalk between conductive layers

A protection circuit using point discharge suitable for use in an integrated circuit, protects circuit from damage by electrostatic discharge. The integrated circuit at least comprises an input/output port, a high voltage line, and a low voltage line. The protection circuit has point discharge structures at two ends of the input/output ports, respectively corresponding to the point discharge structures of the high and low voltage lines, and is suitable for use in all semiconductor fabricating processes.

Electrostatic discharge protection circuit using point discharge

A spike electrostatic discharge (ESD) cavity structure includes an etching stop layer including, for example, polysilicon or metal material. The etching stop layer is used as the etching stop to form an opening in the dielectric layer, inside of which a number of discharging layer pairs are formed. The opening exposes the end portions of the discharge layer pairs. The opening is a cavity and can be vacuumed or filled with air.

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Hsinchu, Taiwan

Shiang Huang-Lu