Taiwan Semiconductor Manufacturing Comp. Ltd.

Applied Materials, Inc.

Other

Shiang-Bau Wang

Ryan Chia-Jen Chen

Chen-Huang Huang

Shu-Yuan Ku

Han-Pin Chung

Ming-Jhe Sie

Shao-Hua Hsu

Hun-Jan Tao

Bor Chiuan Hsieh

Ming-Jie Huang

An Chyi Wei

Cheng-Chung Chang

Ming-Ching Chang

Yan Ye

Douglas A Buchberger, Jr

Wen-Hao Cheng

Yung-Jung Chang

Shu-Uei Jang

Yi-An Huang

Peng-Ren Chen

Li-Wei Yin

Jyun-Hong Chen

Wei-Chung Hu

Chia-Jen Chen

Chun-Hung Lee

Sen-Hong Syue

Szu-Ping Lee

Robert B Hagen

Syun-Ming Jang Jang

Chi-Hsi Wu

Daniel John Hoffman

Ananda H Kumar

Hamid Noorbakhsh

Victor Y Lu

Yuan-Hung Chiu

Steven C Shannon

Matthew L Miller

Gerardo Delgadino

Dan Katz

Xiaoye Zhao

Che-fu Chen

Pu-Fang Chen

Kang-Lie Chiang

Chunshi Cui

Hsu Ming Hsiao

Hong Pin Lin

Kung Shu Hsu

Ta-Wei Kao

Tze-Liang Lee

Yu-Lien Huang

Yen-Yu Chen

Li-Te S Lin

Huan-Just Lin

Liang-Gi Yao

Peng-Fu Hsu

Matt Yeh

Pei-Yu Chou

Meng-Ku Chen

Jin Ying

Chao-Tzung Tsai

Hui Ouyang

Shen H Wang

Chung-chun Ho

Shen Wang

Stephen Thai

David McParland

In a method of manufacturing a semiconductor device, a sacrificial gate structure including sacrificial gate electrode is formed over a substrate. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The recessing the first dielectric layer comprises a first etching operation and a second etching operation using a different etching as from the first etching operation.

Method of manufacturing a semiconductor device and a semiconductor device

A method includes forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding higher than top surfaces of isolation regions. The isolation regions include a portion between the first and the second semiconductor fins. The method further includes forming a gate stack crossing over the first and the second semiconductor fins, etching a portion of the gate stack to form an opening, wherein the portion of the isolation regions, the first semiconductor fin, and the second semiconductor fin are exposed to the opening, etching the first semiconductor fin, the second semiconductor fin, and the portion of the isolation regions to extend the opening into a bulk portion of a semiconductor substrate below the isolation regions, and filling the opening with a dielectric material to form a cut-fin isolation region.

Cut-fin isolation regions and method forming same

In a gate replacement process, a dummy gate and adjacent structure, such as a source/drain region, are formed. The dummy gate is removed, at least in part, using a directional etch to remove some but not all of the dummy gate to form a trench. A portion of the dummy gate remains and protects the adjacent structure. A gate electrode can then be formed in the trench. A two step process can be employed, using an initial isotropic etch followed by the directional etch.

Partial directional etch method and resulting structures

Semiconductor structures are provided. The semiconductor structure includes a substrate and a first fin structure and a second fin structure formed over the substrate. In addition, the second fin structure is higher than the first fin structure. The semiconductor structure further includes an isolation structure formed around the second fin structure and covering a top surface of the first fin structure and a gate structure formed over the first fin structure and the second fin structure. In addition, the top surface of the first fin structure is not flat.

Semiconductor structure with patterned fin structure

In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

Air spacer and method of forming same

A method for shallow trench isolation structures in a semiconductor device and a semiconductor device including the shallow trench isolation structures are disclosed. In an embodiment, the method may include forming a trench in a substrate; depositing a first dielectric liner in the trench; depositing a first shallow trench isolation (STI) material over the first dielectric liner, the first STI material being deposited as a conformal layer; etching the first STI material; depositing a second STI material over the first STI material, the second STI material being deposited as a flowable material; and planarizing the second STI material such that top surfaces of the second STI material are co-planar with top surfaces of the substrate.

Semiconductor device and method

A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.

Semiconductor device and method of manufacture

A method for manufacturing a semiconductor structure includes: forming a semiconductor device on a main region of the device substrate, the device substrate having a peripheral region surrounding the main region; forming a first filling layer on the peripheral region of the device substrate; forming a second filling layer over the first filling layer and the semiconductor device after forming the first filling layer, the second filling layer having a polishing rate different from that of the first filling layer; performing a planarization process over the second filling layer to remove a portion of the second filling layer so that a remaining portion of the second filling layer has a planarized surface opposite to the device substrate; and bonding the device substrate to a carrier substrate through the first filling layer and the remaining portion of the second filling layer.

Wafer bonding method and semiconductor structure obtained by the same

A conductive gate over a semiconductor fin is cut into a first conductive gate and a second conductive gate. An oxide is removed from sidewalls of the first conductive gate and a dielectric material is applied to the sidewalls. Spacers adjacent to the conductive gate are removed to form voids, and the voids are capped with a dielectric material to form air spacers.

Method of manufacturing a semiconductor device

In an embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a side of the gate stack; and a dielectric plug disposed between the CESL and the gate spacer, where the dielectric plug, the CESL, the gate spacer, and the source/drain region collectively define a void physically separating the gate stack from the source/drain region.

Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.

Metal gate structure cutting process

A method for forming a fin field effect transistor (FinFET) device structure and method for forming the same are provided. The method includes providing a substrate, and forming a fin structure on the substrate. The method also includes forming a protection layer on the sidewalls of the fin structure, and forming a dielectric layer on the fin structure and the protection layer. The method further includes removing a portion of the dielectric layer until a portion of the protection layer is exposed, and removing the exposed portion of the protection layer, such that the sidewalls of a lower portion of the fin structure are covered by the protection layer, and the sidewalls of an upper portion of the fin structure are not covered by the protection layer.

Fin field effect transistor (FinFET) device with protection layer

A method of analyzing a semiconductor wafer includes obtaining a graphic data system (GDS) file corresponding to the semiconductor wafer, using GDS information from the GDS file to provide coordinates of a layout feature of the semiconductor wafer to an electron microscope, using the electron microscope to capture a raw image from the semiconductor wafer based on the coordinates of the layout feature, and performing a measurement operation on the raw image.

Semiconductor wafer measurement method and system

Growing community of inventors

Pingzchen, Taiwan

Shiang-Bau Wang