Realtek Semiconductor Inc.

Shian-Ru Lin

Liang-Wei Huang

Chi-Shun Weng

Chao-Cheng Lee

Shieh-Hsing Kuo

Ting-Fa Yu

Ming-Je Li

Shih-Hsiun Huang

Hung-Chen Chu

Yung Tai Chen

A Pre-distortion mechanism for transmit path non-linearity in xDSL AFE is disclosed in the present invention. The AFE includes a line driver and a pre-distortion signal generator. The line driver receives an input differential signal and generates an output differential signal. The input differential signal includes a first input signal and a second input signal. The output differential signal includes a first output signal and a second output signal. The line driver receives the first input signal to generate the first output signal and receives the second input signal to generate the second output signal. The pre-distortion signal generator is coupled to input ends and output ends of the line driver. The pre-distortion signal generator generates a pre-distortion signal according to a first difference between the first input signal and the first output signal, and a second difference between the second input signal and the second output signal so as to adjust an output state of the analog front-end transmitter having a pre-distortion mechanism.

Analog front-end transmitter and a connection method of an X-digital subscriber line having a pre-distortion mechanism

A network processor includes a transceiver circuit, a network data processing unit, and a clock signal control unit. The transceiver circuit transmits and receives a network signal, compares a voltage level of the network signal with a threshold value, outputs a comparison result, and operates under a first clock signal. The network data processing unit is coupled to the transceiver circuit to process the network signal, and operates under a second clock signal different from the first clock signal. The clock signal control unit disables supply of the second clock signal to the network data processing unit when the voltage level is smaller than the threshold value, and enables supply of the second clock signal to the network data processing unit when the voltage level is not smaller than the threshold value. An energy saving method for a network processor is also disclosed.

Network processor and energy saving method thereof

A clock generation device includes a first delay unit, a frequency divider, an angle delay unit and a first calculating unit. The first delay unit receives an input clock and delays the input clock by a first preset period to generate an input delay clock. The frequency divider divides a frequency of the delay clock to generate a first frequency-divided clock and a second frequency-divided clock. A frequency of each of the first frequency-divided clock and the second frequency-divided clock is a preset multiple of the input delay clock. The angle delay unit delays the first frequency-divided clock by a second preset period to generate a first delay clock. The first calculating unit determines a trigger time of a first edge of a first output clock with reference to voltage levels of the first frequency-divided clock and the first delay clock and determines a falling time of a second edge of the first output clock with reference to voltage levels of the input clock and the first delay clock.

Clock generator and method thereof

A power consumption control method applied to a communication system adjusts the power consumption of a portion of circuit in the communication system according to a transmission distance between the communication system and another communication system. Another power consumption control method applied to a communication system adjusts the power consumption of a portion of circuit in the communication system according to a signal index of the communication system.

Power consumption control methods applied to communication systems, and related devices

An integrated circuit (IC) with a low temperature coefficient and an associated calibration method are provided to lower the effect of the environmental temperature on the IC and at the same time to maintain the small area and low power consumption of the IC. The IC includes a first circuit, a second circuit and a calibration control circuit. The first circuit has a low temperature coefficient and generates a first output. The second circuit has a high temperature coefficient and generates a second output. The calibration control circuit detects the first and second outputs, and compares the first and second outputs according to a predefined relationship therebetween so as to generate an adjusting signal. The adjusting signal is for adjusting the second circuit such that the second circuit can have the characteristic of the low temperature coefficient.

Integrated circuit with low temperature coefficient and associated calibration method

A filter circuit is disclosed which comprises a differential amplifier and a switch-capacitor circuit. The invention attains the goals of reducing the power consumption and the circuit size by sharing an amplifier with other related circuits to reduce the number of amplifiers.

Filter circuit and method thereof

A relay set in a network device. The relay includes a first switch, a switch control unit, and a first AC coupling unit. The first switch is coupled between a first receiving end of the network device and a first transmitting end of the network device. The switch control unit is configured to turn off the first switch when the network device is in a first state. The first AC coupling unit is configured to turn on the first switch according to a first signal received from the first receiving end when the network device is in a second state.

Relay set in network device and method thereof

The present invention discloses a multi-phase clock generator of a network controller for generating a set of multi-phase clocks, and a method thereof. The multi-phase clock generator includes a first gating element and a second gating element. The first gating element operates according to a first control clock and generates a first output clock of the set of multi-phase clocks according to an input clock. The second gating element operates according to a second control clock and generates a second output clock of the set of multi-phase clocks according to the first output clock. The second control clock is an inverted signal of the first control clock.

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Nan-Tou Hsien, Taiwan

Shian-Ru Lin