Nan Ya Technology Corporation

Shian-Jyh Lin

Chung-Yuan Lee

Chien-Li Cheng

Pei-Ing Paul Lee

Meng-Hung Chen

Chia-Sheng Yu

Chao-Sung Lai

Jar-Ming Ho

Ming-Yuan Huang

Yu-Pi Lee

Chih-Wei Huang

Ming-Cheng Chang

Neng-Tai Shih

Hai-Han Hung

Hung-Chang Liao

Hsing-Kan Peng

Sam Liao

Shun-Fu Chen

Tse-Chuan Kuo

Yi-Nan Chen

Tzu-Ching Tsai

Chien-Chang Huang

Tean-Sen Jen

Jia-Shyong Cheng

Jeng-Ping Lin

Jui-Hsiu Jao

Yuan-Hsun Wu

Hsin-Jung Ho

Shiou-Yu Wang

Tsang-Po Yang

Wen-Chieh Chang

Jung-Hsing Chien

Tsu-An Lin

Jen-Jui Huang

Sheng-Tsung Chen

An-Hsiung Liu

Yu-Chang Lin

Chin-Piao Chang

Ming-Teng Hsieh

Chien-Jung Yang

Yu-Sheng Shu

Neng Tai Shih

Wen-Sung Tsou

Yi-Jung Chen

Chun-Pin Li

Yu-Sheng Hsu

Sheng-Tsong Chen

Hui-Jen Yang

A semiconductor structure includes a substrate including a substrate including a first surface, a first doped region disposed under the first surface, a second doped region disposed under the first surface, and a recess indented into the substrate and disposed between the first doped region and the second doped region; a control gate structure disposed over the first doped region and electrically connected to a control bit line; a fuse gate structure disposed over the second doped region and electrically connected to a fuse bit line; and a buried word to line disposed between the control gate structure and the fuse gate structure, wherein the buried word line is disposed within the recess of the substrate.

Fuse array structure

A semiconductor memory device includes a substrate, a plurality of landing pads, a first conducting layer, a plurality of first capacitors, a plurality of second capacitors, a second conducting layer and a plurality of third capacitors. The substrate has an active area, and the active area has a first area, a second area and a third area. The third area surrounds the first area. The second area surrounds the first area and the third area. The landing pads are disposed on the first area. The first conducting layer is disposed on the second area. The first capacitors are disposed on the landing pads respectively. The second capacitors are disposed on the first conducting layer. The second conducting layer is disposed on the second capacitors. The third capacitors are disposed in the third area. The second conducting layer is not electrically connected to the third capacitors.

Semiconductor memory device

The present disclosure provides a semiconductor chip. The semiconductor chip includes a substrate, a main device, a one-time-programmable (OTP) device and a decoupling capacitor array. The substrate includes a first region and a second region. The main device is in the first region, the OTP device and the decoupling capacitor array are in the second region, and the decoupling capacitor array overlies the OTP device.

Semiconductor memory device including decoupling capacitor array arranged overlying one-time programmable device

A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of one-time-programmable (OTP) cells, a bottom cell plate, a top cell plate and a decoupling capacitor array. The substrate includes a plurality of active areas and at least one isolation structure provided between the active areas to isolate the active areas from one another. The plurality of OTP cells are disposed in the active areas, the bottom cell plate is disposed on the OTP cells, and the top cell plate is disposed over the bottom cell plate. The decoupling capacitor array is disposed between the bottom cell plate and the top cell plate, and overlies the OTP cells.

A semiconductor structure includes a first anti-fuse structure, a second anti-fuse structure and a first metal layer. The second anti-fuse structure is disposed over the first anti-fuse structure. The first metal layer is between the first anti-fuse structure and the second anti-fuse structure. A first contact is disposed between the first anti-fuse structure and the first metal layer to connect thereof. A second contact is disposed between the second anti-fuse structure and the first metal layer to connect thereof.

Semiconductor structure

A method of manufacturing a semiconductor structure. A patterned first hard mask is formed on a substrate. The patterned first hard mask includes first trench patterns extending along a first direction. A second hard mask is then formed on the patterned first hard mask. A patterned photoresist layer is formed on the second hard mask. The patterned photoresist layer includes second trench patterns extending along a second direction. The second trench patterns intersect first trench patterns. Using the patterned photoresist layer as an etch mask, a first etch process is performed to transfer the second trench patterns into the patterned first hard mask and the second hard mask. Subsequently, using the patterned first hard mask as an etch mask, a second etch process is performed to transfer the first trench patterns and the second trench patterns into the substrate.

Method of manufacturing independent depth-controlled shallow trench isolation

A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO, TiO, ZrO, a germanium nanocrystal layer, an organic charge trapping material, HfSiON, or MoSiON.

Semiconductor device capable of reducing influences of adjacent word lines or adjacent transistors and fabricating method thereof

A method of patterning a metal alloy material layer having hafnium and molybdenum. The method includes forming a patterned mask layer on a metal alloy material layer having hafnium and molybdenum on a substrate. The patterned mask layer is used as a mask and an etching process is performed using an etchant on the metal alloy material layer having hafnium and molybdenum so as to form a metal alloy layer having hafnium and molybdenum. The etchant includes at least nitric acid, hydrofluoric acid and sulfuric acid. The patterned mask layer is removed.

Method of patterning metal alloy material layer having hafnium and molybdenum

A through substrate via having a low stress is provided. The through substrate via is positioned in a substrate. The through substrate via includes: an outer tube penetrating the substrate; at least one inner tube disposed within the outer tube; a dielectric layer lining on a side wall of the outer tube, and a side wall of the inner tube; a strength-enhanced material filling the inner tube; and a conductive layer filling the outer tube.

Method of fabricating a semiconductor device with through substrate via

Semiconductor device with through substrate via

A transistor structure includes a semiconductor substrate having a top surface and sidewalls extending downward from the top surface, wherein each of the sidewall comprises a vertical upper sidewall surface and a lower sidewall recess laterally etched into the semiconductor substrate. A trench fill dielectric region is inlaid into the top surface of the semiconductor substrate. Two source/drain regions are formed into the top surface of the semiconductor substrate and are sandwiched about the trench fill region. A buried gate electrode is embedded in the lower sidewall recess. A gate dielectric layer is formed on surface of the lower sidewall recess between the semiconductor substrate and the buried gate electrode.

DRAM cell with double-gate fin-FET, DRAM cell array and fabrication method thereof

A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench capacitor and extending away from a top surface of the substrate, a first doping region formed on a side of the upper portion of the trench in the substrate for serving as source/drain, a conductive layer formed in the trench and electrically connected to the first doping region, a top dielectric layer formed on conductive layer, a gate formed on the top dielectric layer, an epitaxy layer formed on both sides of the gate and on the substrate and a second doping area formed on a top of the epitaxy layer for serving as source/drain.

Memory device with a length-controllable channel

A trench-type semiconductor device structure is disclosed. The structure includes a semiconductor substrate, a gate dielectric layer and a substrate channel structure. The semiconductor substrate includes a trench having an upper portion and a lower portion. The upper portion includes a conductive layer formed therein. The lower portion includes a trench capacitor formed therein. The gate dielectric layer is located between the semiconductor substrate and the conductive layer. The substrate channel structure with openings, adjacent to the trench, is electrically connected to the semiconductor substrate via the openings.

Trench-type semiconductor device structure

A semiconductor device includes a semiconductor substrate. The semiconductor substrate has a memory array region and a peripheral circuit region; a first active region and a second active region in the peripheral circuit region; a recessed gate disposed on the memory array region, comprising a first gate dielectric layer on the semiconductor substrate, wherein the first gate dielectric layer has a first thickness; and a second gate dielectric layer on the peripheral circuit region, wherein the second gate dielectric layer on the first active layer has a second thickness, and the second gate dielectric layer on the second active layer has a third thickness.

Semiconductor device and fabricating method thereof

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Taipei County, Taiwan

Shian-Jyh Lin