Sun Microsystems, Inc.

Agate Logic, Inc.

Shian-Jiun Fu

Kai Keung Chan

Peter F Lai

Rambabu Pyapali

Aveek Sarkar

Chao-Chiang Chen

David Tsang

A logic processing device, containing an application specific integrated circuit ('ASIC') and field programmable gate array ('FPGA'), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and configurable logic circuit (&#x201c;CLC&#x201d;) wherein the CLC can be an FPGA. While ASIC is able to perform a specific function in accordance with an ASIC clock domain, the CLC is capable of performing a programmable logic function in accordance with an FPGA clock domain. The phase adjustment circuit is used to automatically facilitate a communication between the ASIC and the CLC in accordance with the ASIC clock domain and the FPGA clock domain.

Method and apparatus for facilitating communication between programmable logic circuit and application specific integrated circuit with clock adjustment

The timing response of a circuit path is predicted by modeling the circuit path using two different timing models. The variation between the timing responses produced by each of the timing models is used to generate a correction factor, which is then applied to one of the timing models. Once the correction factor has been applied to a timing model, the model is used to produce a corrected timing prediction for the modeled circuit path.

Method and software for predicting the timing delay of a circuit path using two different timing models

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Sunnyvale, CA, United States of America

Shian-Jiun Fu