Fudan University

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Shi-Li Zhang

Wei Zhang

Fabrice Nemouchi

Dongping Wu

Peng Xu

François Lefloch

Chaochao Fu

Chenyu Wen

Zhaoyang Pi

Na Zhao

Xiangbiao Zhou

Zhen Zhang

A SiGe HBT has an inverted heterojunction structure, where the emitter layer is formed prior to the base layer and the collector layer. The frequency performance of the SiGe HBT is significantly improved through a better thermal process budget for the base profile, essential for higher cut-off frequency (f) and a minimal collector-base area for a reduced parasitic capacitance, essential for higher maximum oscillation frequency (f). This inverted heterojunction structure can be fabricated by using ALE processes to form an emitter on a preformed epitaxial silicide, a base over the emitter and a collector over the base.

Transistor and method of making

The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by forming vias or contact holes in an insulator layer covering the transistor and at metal silicide contact regions corresponding to the source and drain, and by filling the vias with metal-semiconductor compound. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the material in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the source/drain contact regions can be minimized. Furthermore, because the material filling the vias is metal-semiconductor compound, the conducting material in the vias and dielectric material in the insulator layer can form good interface and have good adhesion properties, and the conducting material would not cause structural damage in the dielectric material. Thus, there is no need to form a barrier layer between the insulator layer and the material filling the vias.

Semiconductor device and method of making

An ultra-shallow junction semiconductor field-effect transistor and its methods of making are disclosed. In the present disclosure, a mixture film is formed on a semiconductor substrate with a gate structure formed thereon using a physical vapor deposition (PVD) process, which employs a mixture of metal and semiconductor dopants as a target. The PVD process is followed by annealing, during which ultra-shallow junctions and ultra-thin metal silicide are formed. After removing the mixture film remaining on the semiconductor substrate, an ultra-shallow junction semiconductor field-effect transistor is formed. Because the mixture film comprises metal and semiconductor dopants, ultra-shallow junctions and ultra-thin metal silicide can be formed in a same annealing process. The ultra-shallow junction thus formed can be used in semiconductor field-effect transistors for the 14 nm, 11 nm, or even further technology node.

Ultra-shallow junction semiconductor field-effect transistor and method of making

The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by concurrently formed metal-semiconductor compound contact regions at the source and drain and metal-semiconductor compounds in vias formed at positions corresponding to the source and drain. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the metal-semiconductor compounds in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the metal-semiconductor compound source/drain contact regions can be minimized. Furthermore, because the material filling the vias is metal-semiconductor compound, the conducting material in the vias and dielectric material in the insulator layer can form good interface and have good adhesion properties, and the conducting material would not cause structural damage in the dielectric material. Thus, there is no need to form a barrier layer between the insulator layer and the material filling the vias.

A metal silicide thin film and ultra-shallow junctions and methods of making are disclosed. In the present disclosure, by using a metal and semiconductor dopant mixture as a target, a mixture film is formed on a semiconductor substrate using a physical vapor deposition (PVD) process. The mixture film is removed afterwards by wet etching, which is followed by annealing to form metal silicide thin film and ultra-shallow junctions. Because the metal and semiconductor dopant mixture is used as a target to deposit the mixture film, and the mixture film is removed by wet etching before annealing, self-limiting, ultra-thin, and uniform metal silicide film and ultra-shallow junctions are formed concurrently in semiconductor field-effect transistor fabrication processes, which are suitable for field-effect transistors at the 14 nm, 11 nm, or even further technology node.

Metal silicide thin film, ultra-shallow junctions, semiconductor device and method of making

The present invention provides a charge trapping non-volatile semiconductor memory device and a method of making the device. The charge trapping non-volatile semiconductor memory device comprises a semiconductor substrate, a source region, a drain region, and, consecutively formed over the semiconductor substrate, a channel insulation layer, a charge trapping layer, a blocking insulation layer, and a gate electrode. The drain region includes a P-N junction, and the source region includes a metal-semiconductor junction formed between the semiconductor substrate and a metal including titanium, cobalt, nickel, platinum or one of their various combinations. The charge trapping non-volatile semiconductor memory device according to the present disclosure has low programming voltage, fast programming speed, low energy consumption, and relatively high device reliability.

Method of making a charge trapping non-volatile semiconductor memory device

The present invention provides a floating-gate non-volatile semiconductor memory device and a method of making the same. The floating-gate non-volatile semiconductor memory device comprises a semiconductor substrate, a source, a drain, a first insulator layer, a first polysilicon layer, a second insulator layer, a second polysilicon layer, a protective layer and sidewalls. The source and drain are disposed on the semiconductor substrate. The first insulator layer is disposed over a region of the semiconductor substrate other than regions corresponding to the source and drain. The first polysilicon layer is disposed over the first insulator layer, forming a floating gate. The second insulator layer is disposed over the first polysilicon layer. The second polysilicon layer is disposed over the second insulator layer, forming a control gate and a wordline. The sidewalls are disposed on two sides of the wordline, and the protective layer is disposed over the second polysilicon layer. A semiconductor junction at a drain region is a P-N junction, while a semiconductor junction at a source region is a metal-semiconductor junction.

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Stockholm, Sweden

Shi-Li Zhang