Xilinx, Inc.

Xlinx, Inc.

Shi-dong Zhou

Andy T Nguyen

Gubo Huang

Ronald L Cline

Shankar Lakkapragada

Jack Siu Cheung Lo

Derek R Curd

Tetse Jang

Fariba Farahanchi

Ping Zhang

A programmable differential signaling system includes a programmable bias generator and a plurality of input/output modules. The programmable bias generator is operably coupled to generate a first global bias signal and a second global signal based on desired signal properties of one of a plurality of differential signaling conventions. The a plurality of input/output modules is operably coupled to convert between differential signaling and single ended signaling, wherein actual signal properties of the differential signaling are regulated based on the first and second global bias signals to substantially equal the desired signal properties.

Programmable differential signaling system

A pre-driver for large I/O pull-up and pull-down transistors is provided so that the I/O pull-up and pull-down transistors do not experience crowbar current, and the pre-driver circuit likewise does not experience crowbar current or require large driver transistors. One pre-driver circuit includes two NAND gates and two NOR gates with delay circuitry provided by two series inverters from a data input to a first node, and two additional series inverters from the first node to a second node. A further pre-driver circuit includes feedback from the pre-driver outputs to ensure its NMOS and PMOS transistors do not turn on together to create crowbar, while allowing faster switching. With the pre-driver circuit embodiments, a conventional level shifter can be used. Further with the pre-driver circuitry, slew rate control can be provided in the pull-up and pull-down driver circuitry, rather than in the pre-driver circuitry.

Large loading split I/O driver with negligible crowbar

Low current differential signal/swing I/O interfaces and techniques can be implemented. An output interface converts input data signals to differential current signals for transmission over transmission lines. When the differential current signals are received by an input interface, they are converted to differential voltage signals and appropriately amplified.

Apparatus and method for low current differential swing I/O interface

Apparatus and method for providing reference voltages for differential signaling with tracking of output differential voltage relative to output offset voltage are described. A swing reference voltage, an offset reference voltage, a swing feedback voltage, and an offset feedback voltage are obtained. Differences between pairs of these voltages are differentially amplified to produce first and second bias voltages. Pull-up and pull-down voltages are driven partially responsive to the first bias voltage and the second bias voltage to provide first and second control voltages. The first control voltage may be provided to a first resistance for the driving of the first pull-up and pull-down voltages. The second control voltage may be provided to a second resistance for the driving of the second pull-up and pull-down voltages. The first control voltage and the second control voltage may be provided to a third resistance.

Low voltage differential signaling with output differential voltage to output offset voltage tracking

A test-mode circuit allows the same pad of a semiconductor device to be used as a test pad during test operations and as an I/O pad during normal operations. The test-mode circuit is coupled between the pad and a reference signal (Vbg) of the device, and in response to a control signal (CTRL) either couples the pad and the reference signal (Vbg) together or isolates the pad and the reference signal (Vbg) from each other. The test-mode circuit includes at least one NMOS transistor (MN) and a PMOS transistor (MP) connected in series between the pad and the reference signal (Vbg). During normal operation, the NMOS transistor (MN) isolates the reference signal (Vbg) from the pad, and the PMOS transistor (MP) compensates for voltage undershoot conditions at the pad.

Ground bounce protection circuit for a test mode pin

A power-on reset circuit for generating a reset signal for an associated IC device includes a pull-up resistor connected between a supply voltage and a tracking node, a pull-down transistor connected between the tracking node and ground potential, and a voltage divider circuit connected between the supply voltage and ground potential. The voltage divider circuit has a first ratioed voltage node coupled to the gate of the pull-down transistor. For some embodiments, the voltage divider circuit includes a first resistor connected between the voltage supply and the first ratioed voltage node, a second resistor connected between the first ratioed voltage node and a second ratioed voltage node, a third resistor connected between the second ratioed voltage node and ground potential, and a shunt transistor connected between the second ratioed voltage node and ground potential has a gate responsive to the reset signal.

CMOS power on reset circuit

A configuration control circuit () allows a PLD to be quickly re-configured to implement different functions without requiring any configuration memory cells. The control circuit () includes a first input (IN) connected to a first hardwired configuration bit (HCB), a second input (IN) connected to a second hardwired configuration bit (HCB), an output (OUT) connected to one or more of the PLD's configurable elements (), and a select circuit () to selectively connect either the first input (IN) or the second input (IN) to the output (OUT) in response to a select signal (SEL).

PLD hardwire programming with multiple functional modes

An input circuit includes a first buffer having a first power terminal coupled to a first supply voltage, a second power terminal coupled to ground potential, an input to receive an input signal, and an output to generate a first output signal, a second buffer having a first terminal coupled to a second supply voltage, a second terminal coupled to a bias node, an input to receive the input signal, and an output to generate a second output signal, and a control circuit configured to selectively connect the bias node either to the second supply voltage or to ground potential in response to an enable signal.

Low voltage input circuit with high voltage tolerance capability

A clock selection circuit includes an output multiplexer, control logic, and edge detection logic. The multiplexer includes inputs to receive multiple input clock signals, an output to generate the output clock signal, and a control terminal to receive a synchronized clock select signal. The control logic includes a first input to receive a clock select signal, a second input to receive a first control clock signal, a third input to receive a synchronization signal, and an output to selectively update the synchronized clock select signal with transitions in the clock select signal. The edge detection logic includes first inputs to receive the multiple input clock signals, a second input to receive a second control clock signal, and an output to generate the synchronization signal.

Glitchless clock selection circuit using phase detection switching

A complex programmable logic device (CPLD) that can be scaled upwards in size without unacceptable increases in die size or signal delays. A CPLD includes a two-dimensional array including rows and columns of function blocks and input/output (I/O) blocks programmably interconnected by a de-centralized interconnect structure. The interconnect structure includes numbers of interconnect lines segmented into shorter lengths. Programmable multiplexer circuits couple the segmented interconnect lines to the function blocks and I/O blocks. Programmable switch matrices couple the segmented interconnect lines together into longer interconnect lines of the desired length.

Scalable complex programmable logic device with segmented interconnect resources

Pseudo-differential multiplexer circuits and methods. The circuit input signals are provided to two similar multiplexers, one of which is driven by true signals and one by the complementary input signals. No matter what the values of the circuit input signals, at least one of the two multiplexers always selects a low value. Therefore, at least one of the two multiplexers has the capability of overcoming a value stored in an output circuit (e.g., a latch) coupled to the output terminals of the two multiplexers. Thus, even when neither multiplexer can provide a high signal at the full value of power high VDD, the output circuit provides the correct output value. The invention also encompasses methods of selecting between circuit input signals by utilizing a pseudo-differential multiplexing technique, e.g., utilizing multiplexer circuits similar to those described above.

Structures and methods of implementing a pass gate multiplexer with pseudo-differential input signals

A selectively enabled clamp circuit for limiting voltage overshoot on an input/output (I/O) pin of an associated integrated circuit (IC) device includes a single discharge transistor and a select circuit. The single discharge transistor is connected between the I/O pin and ground potential, and the select circuit is coupled to the I/O pin and includes an input to receive an enable signal and an output coupled to a gate of the signal discharge transistor. For some embodiments, the select circuit includes a level shifter circuit and a voltage detection circuit.

Overvoltage clamp circuit

A technique and circuit implementation are described for automatically detecting a change in a power supply voltage and selectively reconfiguring a circuit for optimized performance at the changed voltage. One application of particular interest is an auto-detect level shifter. The auto-detect level shifter can be used in an output driver and can be automatically enabled if it is needed to optimize performance for various I/O standards, including those that operate at different voltages.

Growing community of inventors

Milpitas, CA, United States of America

Shi-dong Zhou