Motorola Corporation

Shi-Chuan Lee

Alan S Bass

Douglas W Schucker

A BI-CMOS circuit is provided wherein an output terminal is coupled between an upper and lower NPN push-pull transistor. This provides high current drive capability along with no d.c. power dissipation. A P-channel device has a source and a drain connected to the collector and base, respectively, of the upper NPN transistor. An N-channel device has a source and drain connected to the base and collector, respectively, of the lower NPN transistor. The gates of the P-channel and N-channel devices are connected to an input terminal and provide a high impedance thereat. Additional N-channel devices are coupled between the bases of the upper and lower NPN transistors and a supply voltage terminal for improving the switching speed of the output signal.

BI-CMOS driver circuit

A macrocell array is provided wherein a plurality of cells, each having a plurality of semiconductor devices interconnected for providing logic functions, are selectively interconnected to one another and to input/output pads by a plurality of horizontal and vertical routing channels in one or more metallization layers. An on-chip clock generator is provided within one of the cells and comprises a gate means responsive to an input signal and providing a delayed signal. An output means is coupled to the gate means and is responsive to the input signal and the delayed signal for generating a clock pulse. The gate means includes two or more serially connected sets of differentially connected transistors wherein the time between the input signal and the delayed signal is the summation of the propagation delays of the two or more serially connected sets of differentially connected transistors. External override signals allow for control of the clock pulse regardless of the state of the input signal.

Macrocell array having an on-chip clock generator

A macrocell array is provided wherein a plurality of cells, each having a plurality of semiconductor devices interconnected for providing logic functions, are selectively interconnected to one another and to input/output pads by a plurality of horizontal and vertical routing channels in one or more metallization layers. An on-chip diagnostic circuit is provided for diagnosing a plurality of serially connected latches, or flip-flops, in real time. A first logic gate has inputs adapted to receive a data signal and a data enable signal for inputting data into the latches. A second logic gate has inputs adapted to receive a shift-data-in signal and a shift enable signal for shifting the data through the latches. A third logic gate has inputs adapted to receive a hold signal and an output of a first of the plurality of serially connected latches for capturing the states in each of the latches at a given time. A fourth logic gate has inputs adapted to receive a complement enable signal and an output of the first latch for allowing desired test data to simultaneously appear at all the latches under test.

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Mesa, AZ, United States of America

Shi-Chuan Lee