National Taiwan University

United Microelectronics Corp.

Memetics Technology Co. Ltd.

National Science Council

National Applied Research Laboratories

Shey-Shi Lu

Hsien-Ku Chen

Chia-Jung Hsu

Yu-Che Yang

Jen-Chung Chang

Chii-Wann Lin

Hung-Wei Chiu

Tzu-Chao Lin

Chun-Hao Chen

Hsiao-Chin Chen

Yu-Tso Lin

Chih-Kung Lee

Hsin-Hung Liao

Chi-Heng Chang

Ying-Zong Juang

Wei-Tso Lin

Yu-Yee Liow

Chin-Fong Chiu

Pei-Wen Yen

Yao-Joe Yang

Shih-An Yu

Po-Wei Lee

Chih-Ting Lin

Yu-Hao Chen

Da-Chiang Chang

Yeong-Ray Wen

Tsung-Chien Wu

Sheng-Yeh Chou

I-Shun Wang

Kai-Wen Yeh

Yu-Pin Hsu

Nien-Show Ho

Hong-Zong Liao

Yao Joe Yang

Win-Pin Shih

Yu-Jie Huang

Tao Wang

Pen-Li Huang

Che-Wei Huang

Yao-Hong Wang

A biosensor device includes a substrate, a sensing transistor, an isolation layer and a main interface layer. The sensing transistor is formed on the substrate and including a bottom gate structure, a top gate structure and a semiconductor layer disposed between the bottom gate structure and the top gate structure. The bottom gate structure is electrically connected to the top gate structure. The isolation layer is formed on the sensing transistor for covering the sensing transistor, and includes a first opening. The main interface layer is disposed in the first opening for receiving biomolecules to be sensed. The main interface layer is electrically connected to the top gate structure.

Biosensor device

An implantable electrical stimulation system for treating a nerve symptom, the system comprising an implantable device. The implantable devices includes a wave generator that is operable to generate a signal wave and a white noise, mix the signal wave and the white noise, and produce an electrical stimulating signal. The system further comprises an electrode unit located in close proximity to a target nerve and is operable to provide the electrical stimulating signal to the nerve. The system further comprises an external controlling device.

System and method for treating a nerve symptom

A dual mode RF transceiver is provided. The dual mode RF transceiver comprises an antenna, a differential low noise amplifier (LNA), a local oscillator and a dual mode differential mixer. The differential LNA receives an RF signal from the antenna to generate a differential amplified RF signal. The dual mode differential mixer comprises a switch module, a plurality of fundamental mixers and a plurality of sub-harmonic mixers. The fundamental mixers are activated in a first receiving mode to generate a first differential baseband signal according to a multiphase local oscillating (LO) signal from the local oscillator and the differential amplified RF signal. The sub-harmonic mixers are activated in a second receiving mode to generate a second differential baseband signal according to the multiphase LO signal from the local oscillator and the differential amplified RF signal. An RF signal receiving method is disclosed herein as well.

Dual mode RF transceiver and receiving method of the same

A drug-delivery chip and a method of fabricating the same are provided. The drug-delivery chip has a main body having at least one drug receiving space individually formed with an opening for storing drugs therein; a thin film for sealing up the at least one drug receiving space; a first conductive wire connecting to one end of the thin film; a second conductive wire connecting to another end of the thin film; a signal-receiving module for receiving actuated signals; and a control module for applying voltages to first and second wire conductive s according to the actuated signal, thereby generating heat to break off the thin film for the release of a drug or drugs received in the at least one drug receiving space.

Drug delivery chip and fabricating method thereof

The present invention relates to a PLL circuit and an associated method that allows the PLL circuit to operate at a higher operating frequency with a wider bandwidth and a better out-band noise suppression. The PLL circuit comprises a delay locked loop (DLL), a phase-frequency detector (PFD), a loop filter, a voltage controlled oscillator (VCO) and a frequency divider.

Phase-locked loop circuit and an associated method

This invention provides a voltage-controlled oscillator, comprising a first voltage-controlled oscillator circuit and a second voltage-controlled oscillator circuit. The first voltage-controlled oscillator circuit comprises a plurality of inductors, a plurality of variable capacitors, and a plurality of MOS transistors. The circuit configuration of the second voltage-controlled oscillator circuit is symmetrical to that of the first voltage-controlled oscillator circuit. The inductors of the first voltage-controlled oscillator circuit are cross-coupled to the inductors of the second voltage-controlled oscillator circuit.

Voltage-controlled oscillator

The invention includes a harmonic suppression circuit, an injection-locked frequency divider circuit (ILFD) and associated methods. The harmonic suppression circuit comprises a source voltage, two suppression modules, two input terminals, two smoothed output terminals and a ground. The ILFD comprises a ground, an input transistor, an input terminal, two divider legs, two output terminals and a source voltage. The associated method to improve harmonic suppression comprises acts of synthesizing differential-phase signals and simultaneously suppressing second harmonics of in-phase signals. The method to extent an ILFD's locking range comprises acts of decreasing quality factor while keeping resonance frequency constant.

Harmonic suppression circuit, an injection-locked frequency divider circuit and associated methods

The present invention relates to an intra-body communication (IBC) device and a method of implementing the IBC device. The IBC device is fabricated as a system-on-a-chip (SOC) and comprises a first electrode, a second electrode, an IBC module and a biomedical chip. The first electrode is connected to a patient's skin. The second electrode is connected to the patient's skin. The IBC module is connected to the first electrode and comprises a wireless communication device. The biomedical chip is connected to the second electrode and communicates with the IBC module through the patient's skin to receive external commands and transmit sensed biomedical parameters to a faraway location.

Intra-body communication (IBC) device and a method of implementing the IBC device

A multimode millimeter-wave frequency divider circuit with multiple selectable frequency dividing modes is proposed, which is designed for integration with a millimeter wave (MMW) circuit system, such as a phase-locked loop (PLL) circuit, for providing multimode frequency dividing functions. In actual application, the millimeter wave frequency divider circuit of multi frequency dividing mode provides at least three frequency dividing operational modes, including modes of dividing two, dividing 3 and dividing four. In practice, the millimeter wave frequency divider circuit of multi frequency divider mode may be integrated with a millimeter wave phase-locked circuit to provide a frequency synthetic function having multi frequency sections, such as including 38 GHZ, 60 GHZ and 77 GHZ, and may use reduced circuit layout surfaces and operational power.

Multimode millimeter-wave frequency divider circuit with multiple presettable frequency dividing modes

An adapter for RF front end processor chip wherein the RF front end processor chip includes a low noise amplifier which is used to receive a RF filter signal so as to generate a first signal. An adapter is used to receive a first signal so as to induce and generate a second signal and a third signal which is electrically reverse. Then a frequency mixer of the RF front end processor chip is used to receive the second signal and the third signal and a resonant signal, the second signal and the third signal are used to generate a medium frequency signal. Wherein, adapter includes a primary measured coil.

Adapter for the RF front end processor chip

A wideband low noise amplifier. The wideband low noise amplifier comprises an amplifier, an output device, and an inductor. The amplifier amplifies an input signal received from an input node, and outputs the amplified signal to an output node. The output device is coupled to a first voltage and the output node. The peaking inductor is coupled between the amplifier and the output device.

Wideband low noise amplifiers

The present invention is a feed-forward automatic-gain control amplifier (FFAGCA) for biomedical applications and associated method, the FFAGCA comprises a detector, a controller, a variable gain amplifier (VGA), an input and an output. The associated method to process various kinds of biomedical signals with the FFAGCA comprises acts of adjusting gain setting with control path and simultaneously a signal amplification with signal path.

Feed-forward automatic-gain control amplifier (FFAGCA) for biomedical applications and an associated method

A frequency-converting circuit and a down converter with the frequency-converting circuit are disclosed. The above-mentioned frequency-converting circuit is used for converting an RF signal into a first baseband signal according to a poly-phase LO signal. The frequency-converting circuit includes a coupler, a first transduction unit and a first switching unit. The coupler is for receiving and splitting the RF signal and delivering a first RF signal via the first output terminal thereof. The first transduction unit is for amplifying the first RF signal. The first switching unit is for performing switching operations on the output signal of the first transduction unit and producing the first baseband signal.

Frequency-converting circuit and down converter with the same

In a phase locked loop (PLL), phase shifters shift a phase of an input signal. Based on the phases of the input signal, the shifted signals, and a frequency division output signal, phase frequency detectors (PFDs) generate phase difference signals. In response to the phase difference signals, charge pumps (CPs) control output voltages thereof. Based on the output voltages of the CPs, a voltage controlled oscillator (VCO) outputs an output signal. A frequency divider divides the frequency of the output signal from the VCO to generate the frequency division output signal. A circulator outputs the frequency division output signal to one of the PFDs at a proper timing. A modulator reduces quantization errors of the frequency divider.

Phase locked loop with phase shifted input

The provided fractional frequency divider includes a divider controlling unit for generating a divider selection signal in response to a dual-edge triggering of an input signal and a frequency dividing unit coupled to the divider controlling unit for dividing the frequency of the input signal by one of an integer and a fractional dividers in response to the dual-edge triggering and the divider selection signal to generate the output signal of the fractional frequency divider. An operation of the frequency dividing unit is not suppressed when the integer divider is employed, the operation of the frequency dividing unit is not suppressed for a period of the input signal and is suppressed for half of that period, and this cycle is kept on recurring when the fractional divider is employed. The fractional-n PLL having the fractional frequency divider is also provided.

Configuration and controlling method of fractional-N PLL having fractional frequency divider

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Taipei, Taiwan

Shey-Shi Lu