Elpida Memory, Inc.

Shetti Shanmukheshwara Rao

Ankur Goel

Bhawna Tomar

Krishman S Rengarajan

A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the read data, a read circuit for receiving the read data transmitted through the I/O line, and an assist circuit for amplifying the read data transmitted through the I/O line. The assist circuit is disposed farther away from a prescribed drive circuit included in the plurality of drive circuits as viewed from the read circuit. The signal level can thereby rapidly change levels even in memories having relatively long I/O lines.

Semiconductor memory device and method with auxiliary I/O line assist circuit and functionality

A DLL circuit includes a delay line for delaying a clock signal, the delay line including a plurality of cascade-connected variable delay elements, the variable delay elements having a differential circuit structure in which a delay value thereof can be varied by a bias current, a first controller for setting the bias current, and a second controller for selecting an output-producing variable delay element from the plural its of the variable delay elements.

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Bengaluru, India

Shetti Shanmukheshwara Rao