International Business Machines Corporation

Sheshashayee K Raghunathan

Vladimir P Zolotov

Kerim Kalafala

Debjit Sinha

Nathan C Buck

Jin Hu

Jack DiLullo

Thomas S Guzowski

Debra Dean

An electronic design automation (EDA) data processing system includes a version graph database and a controller. The version graph database stores a plurality of different versions of graph data sets. Each graph data set corresponds to a respective circuit component located at a given hierarchical level of a semiconductor chip design and each graph data set tagged with a version identifier (ID) indicating the version thereof. The controller determines a hierarchical circuit included in the semiconductor chip and determines a plurality of targeted circuit components that define the hierarchical circuit. The controller determines targeted graph data sets from the versions graph database that correspond to the targeted circuit components, and obtains the targeted graph data sets having matching version IDs such that the targeted graph data sets are the same version.

Offline analysis of hierarchical electronic design automation derived data

A statistical timing analysis using statistical timing macro-models considering statistical timing value entries such as input slew and output load is disclosed. That statistical timing analysis calculates a statistical timing quantity based on statistical timing value entries based on a statistical timing (ST) macro-model of a selected macro of an integrated circuit (IC) design that includes statistical timing quantities as a function of deterministic timing value entries.

Statistical timing using macro-model considering statistical timing value entry

Growing community of inventors

Bengaluru, India

Sheshashayee K Raghunathan