Sun Microsystems, Inc.

International Business Machines Corporation

Shervin Hojat

Harsh D Sharma

David Hogenmiller

Paul Gerard Villarrubia

Robert E Mains

Matthew J Amatangelo

Jeannette Sutherland

Broadly speaking, a method is provided for evaluating nets in a crosstalk noise analysis. More specifically, a method is provided for evaluating timing window overlap between a pair of nets. The method includes selecting one timing window from each net of the pair of nets for analysis. The method further includes analyzing characteristics of the timing windows selected from the pair of nets to identify a timing window overlap presence, wherein the timing window overlap presence can exist between any two timing windows associated with each net of the pair of nets, respectively.

Method for evaluating nets in crosstalk noise analysis

A blockage aware zero skew clock routing method for calculating the distance, and therefore the delay, between two points takes into account any blockages along the path between the two points and therefore creates a more usable and realistic measure of delay and allows for minimization, or elimination, of clock skew in the system being designed using the method of the invention.

Blockage aware zero skew clock routing method

Devices, methods, and networks that divide and proportionally distribute the drive strength of a clock buffer such that the output drive strength of the clock buffer is divided proportionally among a plurality of outputs from the clock buffer. In one embodiment, the present invention selectively couples adjacent parallel inverters present in a clock buffer to separate, internal distribution wires. The internal distribution wires are selectively coupled to one or more outputs by a connector wire to provide proportional, multiple outputs of the drive strength from the clock buffer to a clock network.

Dividing and distributing the drive strength of a single clock buffer

Coupling capacitance is used to balance skew in a network. In one embodiment, the coupling capacitance exerted by shielding wires oppositely adjacent one or more signal wires in a network is utilized to vary the speed of a signal carried on the one or more signal wires to balance skew in the network.

Use of coupling capacitance to balance skew in a network

One aspect of the invention relates to a method for improving timing convergence in computer aided semiconductor circuit design. In one particular version of the invention, the method includes the steps of generating a behavioral model of a desired semiconductor circuit, which includes timing constraints for individual paths in the circuit, synthesizing the behavioral model to produce a netlist which represents an implementation of the desired semiconductor circuit mapped to a specific semiconductor technology, the netlist including a list of components in the circuit and a list of nets which connect the components in the circuit, and the step of synthesizing includes performing a timing analysis on the implementation so that the paths in the circuit represented by the netlist meet the timing constraints, the timing analysis being performed using estimated wire lengths for the nets. Next, the components in the netlist are placed into an image representing a predefined area of the semiconductor chip. During this step, actual wire lengths are determined for the nets in the netlist. The steps of synthesizing and placing are then repeated until timing convergences is achieved. Each time the step of synthesizing is repeated, the actual wire lengths from the step of placing are substituted for the estimated wire lengths. Finally, the circuit is routed to produce the final design data.

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Austin, TX, United States of America

Shervin Hojat