Intel Corporation

Sherry R Taft

Benjamin Chu-Kung

Sanaz Kabehie Gardner

Marko Radosavljevic

Han Wui Then

Sansaptak W Dasgupta

Seung Hoon Sung

Matthew V Metz

Van H Le

Robert S Chau

Ravi Pillarisetty

Jack T Kavalieros

Gilbert W Dewey

Willy Rachmady

Rafael Rios

Seiyon Kim

Ashish Agrawal

James M Powers

Marc C French

Seung Hoon Hoon Sung

A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. A method including forming a buffer material on a semiconductor substrate, the buffer material including a semiconductor material including a different lattice structure than the substrate; forming a blocking material on the buffer material, the blocking material including a property to inhibit carrier leakage; and forming a transistor device on the substrate. An apparatus including a non-planar multi-gate device on a substrate including a transistor device including a channel disposed on a substrate including a blocking material beneath the channel, the blocking material including a property to inhibit carrier leakage.

Offstate parasitic leakage reduction for tunneling field effect transistors

Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.

Method of fabricating semiconductor structures on dissimilar substrates

A trench comprising a portion of a substrate is formed. A nucleation layer is deposited on the portion of the substrate within the trench. A III-N material layer is deposited on the nucleation layer. The III-N material layer is laterally grown over the trench. A device layer is deposited on the laterally grown III-N material layer. A low defect density region is obtained on the laterally grown material and is used for electronic device fabrication of III-N materials on Si substrates.

III-N devices in Si trenches

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Sherwood, OR, United States of America

Sherry R Taft