Intel Corporation

Sherine Abdelhak

Abhishek R Appu

Joydeep Ray

Altug Koker

Dukhwan Kim

Narayan Biswal

Stanley J Baran

Gokcen Cilingir

Nilesh V Shah

Barnan Das

Archie Sharma

Mayuresh M Varerkar

Junhai Qiu

Shravan Kumar Belagal Math

Neelay Pandit

Ajit P Joshi

Nandini Mahendran

John Charles Weast

Linda L Hurd

Mike MacPherson

Praneetha Kotha

Prasoonkumar Surti

Jill MacDonald Boyce

Vasanth Ranganathan

Varghese George

Sanjeev S Jahagirdar

Narayan Srinivasa

Anbang Yao

Feng Chen

Adam T Lake

Carl S Marshall

Scott R Janus

Tatiana Shpeisman

Xiaoming Chen

Vallabhajosyula S Somayazulu

Ping Tak Tang

Nadathur Rajagopalan Satish

Deepak Shashidhar Vembar

Selvakumar Panneer

Karthik Veeramani

Hugues Labbe

Michael S Strickland

Mike B Macpherson

Farshad Akhbari

Zhijun Lei

Zhengmin Li

Sachin B Godse

Darrel K Palke

Jun Jiang

Tamoghna Ghosh

One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.

Graphics architecture including a neural network pipeline

A graphics processor can include a processing cluster array including a plurality of processing clusters coupled with the plurality of memory controllers, each processing cluster of the plurality of processing clusters including a plurality of streaming multiprocessors, the processing cluster array configured for partitioning into a plurality of partitions. The plurality of partitions include a first partition including a first plurality of streaming multiprocessors configured to perform operations for a first neural network, The operations for the first neural network are isolated to the first partition. The plurality of partitions also include a second partition including a second plurality of streaming multiprocessors configured to perform operations for a second neural network. The operations for the second neural network are isolated to the second partition and protected from operations performed for the first neural network.

Graphics neural network processor, method, and system

Methods, apparatus, systems and articles of manufacture to generate temporal representations for action recognition systems are disclosed. An example apparatus includes an optical flow computer to compute first optical flows for a video based on computing differences between pairs of frames of the video; an evolution of trajectories (EoT) generator to generate EoT temporal representations of the video based on (a) computing second optical flows of the video and (b) aggregating ones of the second optical flows having different time spans; an action identifier to: identify first actions in the video based on the first optical flows; identify second actions in the video based on the EoT temporal representations; and identify third actions in the video based on frames of the video; and a fuser to determine a fourth action based on a weighted average of the first actions, second actions, and third actions.

Methods and apparatus to generate temporal representations for action recognition systems

One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.

The present disclosure is directed to systems and methods of optimizing display image quality on display devices having a plurality of display power modes. An example apparatus includes processor circuitry to execute instructions to: determine a baseline allowable percentage of distorted pixels for a power mode of a display; determine a baseline first relationship between an original pixel value and a boosted pixel value for the power mode; determine a baseline second relationship based on the baseline allowable percentage and the baseline first relationship; select a plurality of test distorted pixel percentages; determine, for respective selected test distorted pixel percentages, a corresponding test relationship between an original pixel color value distribution and a boosted pixel color value distribution based on the baseline second relationship; determine, for respective test relationships, a respective test peak signal to noise ratio (PSNR); determine, for the respective test PSNRs, respective values indicative of the change in image quality for the test distorted pixel percentages; and select, as the operating distorted original pixel percentage value, one of the test distorted pixel percentages based on the values.

Power saving display having improved image quality

A mechanism is described for facilitating recognition, reidentification, and security in machine learning at autonomous machines. A method of embodiments, as described herein, includes facilitating a camera to detect one or more objects within a physical vicinity, the one or more objects including a person, and the physical vicinity including a house, where detecting includes capturing one or more images of one or more portions of a body of the person. The method may further include extracting body features based on the one or more portions of the body, comparing the extracted body features with feature vectors stored at a database, and building a classification model based on the extracted body features over a period of time to facilitate recognition or reidentification of the person independent of facial recognition of the person.

Recognition, reidentification and security enhancements using autonomous machines

A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.

Hybrid graphics processor-field programmable gate array system

Example display power management control circuitry is to determine a baseline image quality parameter associated with a baseline display power mode based on: a baseline first relationship parameter associated with a first relationship between original and boosted pixel values; a baseline percentage of pixels having a color value; and a baseline second relationship parameter associated with a second relationship between the numbers of original pixel values and boosted pixel values; determine a value of a subsequent first relationship parameter based on an adjusted second relationship parameter and a second percentage of pixels having the color value; determine a second image quality parameter associated with the subsequent first relationship parameter, the adjusted second relationship parameter, and the second percentage of pixels; and select the subsequent first relationship parameter and the adjusted second relationship parameter based on comparing the second image quality parameter to the baseline image quality parameter.

Systems and methods of reducing display power consumption with minimal effect on image quality

The present disclosure is directed to systems and methods for reducing display image power consumption while maintaining a consistent, objectively measurable, level of image distortion that comports with a display image quality metric. Raw image data is converted to an HSV format. 'V' values are extracted from the HSV format raw image data and a histogram generates a plurality of 'V' values. HSV format raw image data is provided to at least one layer of a trained CNN to extract a plurality of features. The plurality of &#x201c;V&#x201d; values and the plurality of features are provided to an AI circuit to generate a plurality of distortion class value pairs. Each of the distortion class value pairs is weighted based on proximity of display image distortion and the display image quality metric. The distortion class pair providing a display image distortion close to the display image quality metric is applied to the raw image data to generate the display image data.

Content adaptive display power savings systems and methods

The present disclosure is directed to systems and methods of optimizing display image quality on display devices having a plurality of display power modes. Each power mode has associated therewith a respective baseline allowable percentage of distorted pixels and a baseline first relationship between an original pixel value and boosted pixel value. Display control circuitry determines a baseline second relationship using the baseline percentage of distorted pixels and the baseline first relationship. The display control circuitry selects a plurality of test distorted original pixel values and determines a respective test first relationship. Using the test distorted original pixel value, the respective test first relationship, and the baseline second relationship, the display control circuitry determines a respective PSNR and value indicative of the change in display image quality for each of the test distorted original pixel values.

The present disclosure is directed to systems and methods of reducing display image power consumption while maintaining image quality on display devices having a plurality of display power modes. Each display power mode has associated therewith a defined baseline value (K) first relationship. A display image includes a baseline percentage under-boosted pixels (X). Using the first relationship value (K) and the pixel percentage (X), a baseline second relationship value is determined (K). The value associated with the second relationship is adjusted to a first plurality of values. At each value, the value associated with the pixel percentage is adjusted to each of a second plurality of values. At each combination of second relationship value and pixel percentage, a respective first relationship value is determined. A first relationship value, second relationship value are selected to provide a reduced power consumption while maintaining image quality.

Person tracking and privacy and acceleration of data using autonomous machines

Growing community of inventors

Beaverton, OR, United States of America

Sherine Abdelhak